Search

Jeffery Shawn Zweizig

Examiner (ID: 5312, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2842, 2849, 2504
Total Applications
2641
Issued Applications
2460
Pending Applications
70
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4576678 [patent_doc_number] => 07822953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Protection of a program against a trap' [patent_app_type] => utility [patent_app_number] => 11/717225 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3896 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/822/07822953.pdf [firstpage_image] =>[orig_patent_app_number] => 11717225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717225
Protection of a program against a trap Mar 12, 2007 Issued
Array ( [id] => 4825918 [patent_doc_number] => 20080229062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Method of sharing registers in a processor and processor' [patent_app_type] => utility [patent_app_number] => 11/716990 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4972 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229062.pdf [firstpage_image] =>[orig_patent_app_number] => 11716990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716990
Method of sharing registers in a processor and processor Mar 11, 2007 Abandoned
Array ( [id] => 163320 [patent_doc_number] => 07676658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Data processing apparatus configured to load a program corresponding to each of a plurality of functions into a memory and execute the loaded program, and method for loading programs in the data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/684905 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 12524 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676658.pdf [firstpage_image] =>[orig_patent_app_number] => 11684905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684905
Data processing apparatus configured to load a program corresponding to each of a plurality of functions into a memory and execute the loaded program, and method for loading programs in the data processing apparatus Mar 11, 2007 Issued
Array ( [id] => 4700208 [patent_doc_number] => 20080222392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method and arrangements for pipeline processing of instructions' [patent_app_type] => utility [patent_app_number] => 11/716153 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222392.pdf [firstpage_image] =>[orig_patent_app_number] => 11716153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716153
Method and arrangements for pipeline processing of instructions Mar 8, 2007 Abandoned
Array ( [id] => 4700209 [patent_doc_number] => 20080222393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method and arrangements for pipeline processing of instructions' [patent_app_type] => utility [patent_app_number] => 11/716373 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222393.pdf [firstpage_image] =>[orig_patent_app_number] => 11716373 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716373
Method and arrangements for pipeline processing of instructions Mar 8, 2007 Abandoned
Array ( [id] => 234887 [patent_doc_number] => 07600099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'System and method for predictive early allocation of stores in a microprocessor' [patent_app_type] => utility [patent_app_number] => 11/683843 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3990 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600099.pdf [firstpage_image] =>[orig_patent_app_number] => 11683843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683843
System and method for predictive early allocation of stores in a microprocessor Mar 7, 2007 Issued
Array ( [id] => 8208015 [patent_doc_number] => 08190861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Micro-sequence based security model' [patent_app_type] => utility [patent_app_number] => 11/677367 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4728 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190861.pdf [firstpage_image] =>[orig_patent_app_number] => 11677367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677367
Micro-sequence based security model Feb 20, 2007 Issued
Array ( [id] => 5221416 [patent_doc_number] => 20070162728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded' [patent_app_type] => utility [patent_app_number] => 11/703225 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11787 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20070162728.pdf [firstpage_image] =>[orig_patent_app_number] => 11703225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703225
Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded Feb 6, 2007 Abandoned
Array ( [id] => 180050 [patent_doc_number] => 07657766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Apparatus for an energy efficient clustered micro-architecture' [patent_app_type] => utility [patent_app_number] => 11/698612 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6007 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657766.pdf [firstpage_image] =>[orig_patent_app_number] => 11698612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698612
Apparatus for an energy efficient clustered micro-architecture Jan 25, 2007 Issued
Array ( [id] => 5064819 [patent_doc_number] => 20070226461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device' [patent_app_type] => utility [patent_app_number] => 11/657392 [patent_app_country] => US [patent_app_date] => 2007-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12347 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226461.pdf [firstpage_image] =>[orig_patent_app_number] => 11657392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657392
Reverse polish notation device for handling tables, and electronic integrated circuit including such a processing device Jan 23, 2007 Abandoned
Array ( [id] => 4905555 [patent_doc_number] => 20080114969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Instructions for efficiently accessing unaligned partial vectors' [patent_app_type] => utility [patent_app_number] => 11/655656 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20080114969.pdf [firstpage_image] =>[orig_patent_app_number] => 11655656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/655656
Instructions for efficiently accessing unaligned partial vectors Jan 17, 2007 Issued
Array ( [id] => 4754803 [patent_doc_number] => 20080162879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Methods and apparatuses for aligning and/or executing instructions' [patent_app_type] => utility [patent_app_number] => 11/648156 [patent_app_country] => US [patent_app_date] => 2006-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 14456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162879.pdf [firstpage_image] =>[orig_patent_app_number] => 11648156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648156
Methods and apparatuses for aligning and/or executing instructions Dec 29, 2006 Abandoned
Array ( [id] => 4754834 [patent_doc_number] => 20080162910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Asynchronous control transfer' [patent_app_type] => utility [patent_app_number] => 11/648187 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5467 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162910.pdf [firstpage_image] =>[orig_patent_app_number] => 11648187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648187
Asynchronous control transfer Dec 28, 2006 Issued
Array ( [id] => 38219 [patent_doc_number] => 07788473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Prediction of data values read from memory by a microprocessor using the storage destination of a load operation' [patent_app_type] => utility [patent_app_number] => 11/646008 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 13723 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788473.pdf [firstpage_image] =>[orig_patent_app_number] => 11646008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646008
Prediction of data values read from memory by a microprocessor using the storage destination of a load operation Dec 25, 2006 Issued
Array ( [id] => 4585802 [patent_doc_number] => 07856548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-21 [patent_title] => 'Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold' [patent_app_type] => utility [patent_app_number] => 11/645901 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 13680 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856548.pdf [firstpage_image] =>[orig_patent_app_number] => 11645901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645901
Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold Dec 25, 2006 Issued
Array ( [id] => 313140 [patent_doc_number] => 07529918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor' [patent_app_type] => utility [patent_app_number] => 11/643787 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9470 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529918.pdf [firstpage_image] =>[orig_patent_app_number] => 11643787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643787
System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor Dec 21, 2006 Issued
Array ( [id] => 4606361 [patent_doc_number] => 07987347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'System and method for implementing a zero overhead loop' [patent_app_type] => utility [patent_app_number] => 11/643998 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5509 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987347.pdf [firstpage_image] =>[orig_patent_app_number] => 11643998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643998
System and method for implementing a zero overhead loop Dec 21, 2006 Issued
Array ( [id] => 4616532 [patent_doc_number] => 07991985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'System and method for implementing and utilizing a zero overhead loop' [patent_app_type] => utility [patent_app_number] => 11/644000 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5207 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/991/07991985.pdf [firstpage_image] =>[orig_patent_app_number] => 11644000 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644000
System and method for implementing and utilizing a zero overhead loop Dec 21, 2006 Issued
Array ( [id] => 4589554 [patent_doc_number] => 07861069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'System and method for handling load and/or store operations in a superscalar microprocessor' [patent_app_type] => utility [patent_app_number] => 11/640968 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10915 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861069.pdf [firstpage_image] =>[orig_patent_app_number] => 11640968 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640968
System and method for handling load and/or store operations in a superscalar microprocessor Dec 18, 2006 Issued
Array ( [id] => 7798395 [patent_doc_number] => 08127113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-28 [patent_title] => 'Generating hardware accelerators and processor offloads' [patent_app_type] => utility [patent_app_number] => 11/607452 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 40 [patent_no_of_words] => 12465 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127113.pdf [firstpage_image] =>[orig_patent_app_number] => 11607452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607452
Generating hardware accelerators and processor offloads Nov 30, 2006 Issued
Menu