Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1226254 [patent_doc_number] => 06700436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method and circuit for generating a high voltage' [patent_app_type] => B2 [patent_app_number] => 10/246036 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5063 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700436.pdf [firstpage_image] =>[orig_patent_app_number] => 10246036 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246036
Method and circuit for generating a high voltage Sep 16, 2002 Issued
Array ( [id] => 1246994 [patent_doc_number] => 06677815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Second order active RC filter with imaginary zero' [patent_app_type] => B1 [patent_app_number] => 10/245177 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1632 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677815.pdf [firstpage_image] =>[orig_patent_app_number] => 10245177 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245177
Second order active RC filter with imaginary zero Sep 16, 2002 Issued
Array ( [id] => 6719585 [patent_doc_number] => 20030053273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Electronic device having a CMOS circuit' [patent_app_type] => new [patent_app_number] => 10/245413 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5582 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20030053273.pdf [firstpage_image] =>[orig_patent_app_number] => 10245413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245413
Electronic device having a CMOS circuit Sep 16, 2002 Issued
Array ( [id] => 6718973 [patent_doc_number] => 20030052660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Internal step-down power supply circuit' [patent_app_type] => new [patent_app_number] => 10/243644 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8017 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20030052660.pdf [firstpage_image] =>[orig_patent_app_number] => 10243644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243644
Internal step-down power supply circuit Sep 15, 2002 Issued
Array ( [id] => 743665 [patent_doc_number] => 07030682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Voltage detection circuit and internal voltage generating circuit comprising it' [patent_app_type] => utility [patent_app_number] => 10/489106 [patent_app_country] => US [patent_app_date] => 2002-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 19211 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030682.pdf [firstpage_image] =>[orig_patent_app_number] => 10489106 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/489106
Voltage detection circuit and internal voltage generating circuit comprising it Sep 10, 2002 Issued
Array ( [id] => 1154620 [patent_doc_number] => 06771114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Charge pump current compensating circuit' [patent_app_type] => B2 [patent_app_number] => 10/237946 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771114.pdf [firstpage_image] =>[orig_patent_app_number] => 10237946 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/237946
Charge pump current compensating circuit Sep 8, 2002 Issued
Array ( [id] => 1285718 [patent_doc_number] => 06642781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Selectable equalization system and method' [patent_app_type] => B1 [patent_app_number] => 10/236761 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4354 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642781.pdf [firstpage_image] =>[orig_patent_app_number] => 10236761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236761
Selectable equalization system and method Sep 5, 2002 Issued
Array ( [id] => 1222488 [patent_doc_number] => 06703892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Mechanism for coupling a wideband current signal between two different potentials' [patent_app_type] => B1 [patent_app_number] => 10/236672 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2192 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703892.pdf [firstpage_image] =>[orig_patent_app_number] => 10236672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236672
Mechanism for coupling a wideband current signal between two different potentials Sep 5, 2002 Issued
Array ( [id] => 1218639 [patent_doc_number] => 06707333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Bias circuit' [patent_app_type] => B2 [patent_app_number] => 10/234479 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7298 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707333.pdf [firstpage_image] =>[orig_patent_app_number] => 10234479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/234479
Bias circuit Sep 4, 2002 Issued
Array ( [id] => 6318525 [patent_doc_number] => 20020196059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Memory system including a memory device having a controlled output driver characteristic' [patent_app_type] => new [patent_app_number] => 10/230931 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6403 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196059.pdf [firstpage_image] =>[orig_patent_app_number] => 10230931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230931
Memory system including a memory device having a controlled output driver characteristic Aug 28, 2002 Issued
Array ( [id] => 1278110 [patent_doc_number] => 06650187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Decision directed suppressed carrier symbol-rate PLL with programmable phase discriminator and chip-rate phase extrapolation' [patent_app_type] => B1 [patent_app_number] => 10/233246 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5044 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650187.pdf [firstpage_image] =>[orig_patent_app_number] => 10233246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233246
Decision directed suppressed carrier symbol-rate PLL with programmable phase discriminator and chip-rate phase extrapolation Aug 28, 2002 Issued
Array ( [id] => 7632474 [patent_doc_number] => 06664861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method and apparatus for stable phase-locked looping' [patent_app_type] => B2 [patent_app_number] => 10/232448 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5601 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664861.pdf [firstpage_image] =>[orig_patent_app_number] => 10232448 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232448
Method and apparatus for stable phase-locked looping Aug 27, 2002 Issued
Array ( [id] => 7624927 [patent_doc_number] => 06724244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Stable current source circuit with compensation circuit' [patent_app_type] => B2 [patent_app_number] => 10/227811 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2455 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724244.pdf [firstpage_image] =>[orig_patent_app_number] => 10227811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227811
Stable current source circuit with compensation circuit Aug 26, 2002 Issued
Array ( [id] => 1173082 [patent_doc_number] => 06753719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'System and circuit for controlling well biasing and method thereof' [patent_app_type] => B2 [patent_app_number] => 10/227893 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3887 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753719.pdf [firstpage_image] =>[orig_patent_app_number] => 10227893 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227893
System and circuit for controlling well biasing and method thereof Aug 25, 2002 Issued
Array ( [id] => 6837482 [patent_doc_number] => 20030034822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Local supply generator for a digital cmos integrated circuit having an analog signal processing circuitry' [patent_app_type] => new [patent_app_number] => 10/204745 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3843 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034822.pdf [firstpage_image] =>[orig_patent_app_number] => 10204745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/204745
Local supply generator for a digital CMOS integrated circuit having an analog signal processing circuitry Aug 22, 2002 Issued
Array ( [id] => 1273792 [patent_doc_number] => 06653892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Squelch circuit to create a squelch waveform for USB 2.0' [patent_app_type] => B2 [patent_app_number] => 10/226057 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3911 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653892.pdf [firstpage_image] =>[orig_patent_app_number] => 10226057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226057
Squelch circuit to create a squelch waveform for USB 2.0 Aug 21, 2002 Issued
Array ( [id] => 1246969 [patent_doc_number] => 06677803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 10/224420 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6250 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677803.pdf [firstpage_image] =>[orig_patent_app_number] => 10224420 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224420
Semiconductor integrated circuit device Aug 20, 2002 Issued
Array ( [id] => 1289829 [patent_doc_number] => 06639481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Transformer coupled quadrature tuned oscillator' [patent_app_type] => B1 [patent_app_number] => 10/224684 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639481.pdf [firstpage_image] =>[orig_patent_app_number] => 10224684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224684
Transformer coupled quadrature tuned oscillator Aug 19, 2002 Issued
Array ( [id] => 6318565 [patent_doc_number] => 20020196068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'A Bus Agent Utilizing Dynamic Biasing Circuitry to Translate a Signal to a Core Voltage Level' [patent_app_type] => new [patent_app_number] => 10/199160 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5459 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20020196068.pdf [firstpage_image] =>[orig_patent_app_number] => 10199160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/199160
Bus agent utilizing dynamic biasing circuitry to translate a signal to a core voltage level Jul 17, 2002 Issued
Array ( [id] => 6714204 [patent_doc_number] => 20030025552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/193910 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 17085 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025552.pdf [firstpage_image] =>[orig_patent_app_number] => 10193910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193910
Semiconductor integrated circuit for holding an output signal of an output terminal in a non-operating state Jul 14, 2002 Issued
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