
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6686761
[patent_doc_number] => 20030030484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Low-power high-performance integrated circuit and related methods'
[patent_app_type] => new
[patent_app_number] => 10/155490
[patent_app_country] => US
[patent_app_date] => 2002-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8074
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20030030484.pdf
[firstpage_image] =>[orig_patent_app_number] => 10155490
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155490 | Low-power high-performance integrated circuit and related methods | May 21, 2002 | Issued |
Array
(
[id] => 6107864
[patent_doc_number] => 20020171462
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Power-on/off reset circuit'
[patent_app_type] => new
[patent_app_number] => 10/145270
[patent_app_country] => US
[patent_app_date] => 2002-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0171/20020171462.pdf
[firstpage_image] =>[orig_patent_app_number] => 10145270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/145270 | Power-on/off reset circuit | May 13, 2002 | Issued |
Array
(
[id] => 1207516
[patent_doc_number] => 06717450
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-06
[patent_title] => 'Monolithic I-load architecture for automatic test equipment'
[patent_app_type] => B1
[patent_app_number] => 10/144175
[patent_app_country] => US
[patent_app_date] => 2002-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/717/06717450.pdf
[firstpage_image] =>[orig_patent_app_number] => 10144175
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/144175 | Monolithic I-load architecture for automatic test equipment | May 12, 2002 | Issued |
Array
(
[id] => 1345939
[patent_doc_number] => 06590443
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-08
[patent_title] => 'Dynamic biasing for cascoded transistors to double operating supply voltage'
[patent_app_type] => B1
[patent_app_number] => 10/144946
[patent_app_country] => US
[patent_app_date] => 2002-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/590/06590443.pdf
[firstpage_image] =>[orig_patent_app_number] => 10144946
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/144946 | Dynamic biasing for cascoded transistors to double operating supply voltage | May 12, 2002 | Issued |
Array
(
[id] => 7634143
[patent_doc_number] => 06657477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-02
[patent_title] => 'Integrated circuit'
[patent_app_type] => B2
[patent_app_number] => 10/139197
[patent_app_country] => US
[patent_app_date] => 2002-05-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/657/06657477.pdf
[firstpage_image] =>[orig_patent_app_number] => 10139197
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/139197 | Integrated circuit | May 5, 2002 | Issued |
Array
(
[id] => 1354210
[patent_doc_number] => 06580313
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'System and method for providing single pin bypass for multiple circuits'
[patent_app_type] => B1
[patent_app_number] => 10/138356
[patent_app_country] => US
[patent_app_date] => 2002-05-03
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/580/06580313.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138356 | System and method for providing single pin bypass for multiple circuits | May 2, 2002 | Issued |
Array
(
[id] => 1025862
[patent_doc_number] => 06885233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-26
[patent_title] => 'Altering operating frequency and voltage set point of a circuit in response to the operating temperature and instantaneous operating voltage of the circuit'
[patent_app_type] => utility
[patent_app_number] => 10/138345
[patent_app_country] => US
[patent_app_date] => 2002-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2952
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/885/06885233.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138345
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138345 | Altering operating frequency and voltage set point of a circuit in response to the operating temperature and instantaneous operating voltage of the circuit | May 1, 2002 | Issued |
Array
(
[id] => 6723733
[patent_doc_number] => 20030206045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'LOCALIZED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT INPUT/OUTPUT PADS'
[patent_app_type] => new
[patent_app_number] => 10/138463
[patent_app_country] => US
[patent_app_date] => 2002-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0206/20030206045.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138463
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138463 | Localized electrostatic discharge protection for integrated circuit input/output pads | May 1, 2002 | Issued |
Array
(
[id] => 1307417
[patent_doc_number] => 06621329
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-16
[patent_title] => 'Semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/134428
[patent_app_country] => US
[patent_app_date] => 2002-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/621/06621329.pdf
[firstpage_image] =>[orig_patent_app_number] => 10134428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/134428 | Semiconductor device | Apr 29, 2002 | Issued |
Array
(
[id] => 6764329
[patent_doc_number] => 20030098727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-29
[patent_title] => 'Starter circuit'
[patent_app_type] => new
[patent_app_number] => 10/134618
[patent_app_country] => US
[patent_app_date] => 2002-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2517
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20030098727.pdf
[firstpage_image] =>[orig_patent_app_number] => 10134618
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/134618 | Starter circuit | Apr 29, 2002 | Issued |
Array
(
[id] => 6318575
[patent_doc_number] => 20020196071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Current reference circuit for low supply voltages'
[patent_app_type] => new
[patent_app_number] => 10/133216
[patent_app_country] => US
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[pdf_file] => publications/A1/0196/20020196071.pdf
[firstpage_image] =>[orig_patent_app_number] => 10133216
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/133216 | Current reference circuit for low supply voltages | Apr 25, 2002 | Issued |
Array
(
[id] => 5783521
[patent_doc_number] => 20020158683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Circuit arrangement to reduce the supply voltage of a circuit part and process for activating a circuit part'
[patent_app_type] => new
[patent_app_number] => 10/132502
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10132502
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/132502 | Circuit arrangement to reduce the supply voltage of a circuit part and process for activating a circuit part | Apr 24, 2002 | Issued |
Array
(
[id] => 7623374
[patent_doc_number] => 06686791
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Oxide anti-fuse structure utilizing high voltage transistors'
[patent_app_type] => B2
[patent_app_number] => 10/131141
[patent_app_country] => US
[patent_app_date] => 2002-04-25
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[pdf_file] => patents/06/686/06686791.pdf
[firstpage_image] =>[orig_patent_app_number] => 10131141
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/131141 | Oxide anti-fuse structure utilizing high voltage transistors | Apr 24, 2002 | Issued |
Array
(
[id] => 1407216
[patent_doc_number] => 06531915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-11
[patent_title] => 'Biasing scheme for low supply headroom applications'
[patent_app_type] => B2
[patent_app_number] => 10/127752
[patent_app_country] => US
[patent_app_date] => 2002-04-23
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531915.pdf
[firstpage_image] =>[orig_patent_app_number] => 10127752
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/127752 | Biasing scheme for low supply headroom applications | Apr 22, 2002 | Issued |
Array
(
[id] => 6430700
[patent_doc_number] => 20020175748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Filter circuit and electronic device using the same'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10125532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/125532 | Filter circuit and electronic device using the same | Apr 18, 2002 | Issued |
Array
(
[id] => 6695235
[patent_doc_number] => 20030107429
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'Current source circuit'
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[pdf_file] => publications/A1/0107/20030107429.pdf
[firstpage_image] =>[orig_patent_app_number] => 10125409
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/125409 | Current source circuit | Apr 18, 2002 | Abandoned |
Array
(
[id] => 1367175
[patent_doc_number] => 06573768
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[patent_kind] => B2
[patent_issue_date] => 2003-06-03
[patent_title] => 'Power-on circuit of a peripheral component'
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[pdf_file] => patents/06/573/06573768.pdf
[firstpage_image] =>[orig_patent_app_number] => 10125139
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/125139 | Power-on circuit of a peripheral component | Apr 17, 2002 | Issued |
Array
(
[id] => 6873066
[patent_doc_number] => 20030193363
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[patent_kind] => A1
[patent_issue_date] => 2003-10-16
[patent_title] => 'SEQUENCING CIRCUIT FOR APPLYING A HIGHEST VOLTAGE SOURCE TO A CHIP'
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[patent_app_number] => 10/122994
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[firstpage_image] =>[orig_patent_app_number] => 10122994
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/122994 | Sequencing circuit for applying a highest voltage source to a chip | Apr 14, 2002 | Issued |
Array
(
[id] => 1303563
[patent_doc_number] => 06624684
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[patent_title] => 'Compact high voltage solid state switch'
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[pdf_file] => patents/06/624/06624684.pdf
[firstpage_image] =>[orig_patent_app_number] => 10121643
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/121643 | Compact high voltage solid state switch | Apr 11, 2002 | Issued |
Array
(
[id] => 1349262
[patent_doc_number] => 06586985
[patent_country] => US
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[patent_issue_date] => 2003-07-01
[patent_title] => 'Methods and apparatus for trimming packaged electrical devices'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/586/06586985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10122608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/122608 | Methods and apparatus for trimming packaged electrical devices | Apr 11, 2002 | Issued |