Search

Jeffery Shawn Zweizig

Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2849, 2842, 2504
Total Applications
2640
Issued Applications
2460
Pending Applications
67
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6691241 [patent_doc_number] => 20030038673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/096426 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6736 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038673.pdf [firstpage_image] =>[orig_patent_app_number] => 10096426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096426
Semiconductor device Mar 12, 2002 Issued
Array ( [id] => 6076787 [patent_doc_number] => 20020079952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'SELF INITIALIZATION FOR CHARGE PUMPS' [patent_app_type] => new [patent_app_number] => 10/051696 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4819 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079952.pdf [firstpage_image] =>[orig_patent_app_number] => 10051696 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051696
Self initialization forcharge pumps Jan 16, 2002 Issued
Array ( [id] => 6855059 [patent_doc_number] => 20030128560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'High voltage generation and regulation system for digital multilevel nonvolatile memory' [patent_app_type] => new [patent_app_number] => 10/044273 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9445 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20030128560.pdf [firstpage_image] =>[orig_patent_app_number] => 10044273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044273
High voltage generation and regulation system for digital multilevel nonvolatile memory Jan 9, 2002 Issued
Array ( [id] => 6285807 [patent_doc_number] => 20020053941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Transmission gate' [patent_app_type] => new [patent_app_number] => 10/029299 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053941.pdf [firstpage_image] =>[orig_patent_app_number] => 10029299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029299
Transmission gate Dec 27, 2001 Issued
Array ( [id] => 1329465 [patent_doc_number] => 06603345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Semiconductor device with reduced leakage of current' [patent_app_type] => B2 [patent_app_number] => 10/033628 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11556 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603345.pdf [firstpage_image] =>[orig_patent_app_number] => 10033628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033628
Semiconductor device with reduced leakage of current Dec 27, 2001 Issued
Array ( [id] => 1387805 [patent_doc_number] => 06559707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Bootstrap circuit' [patent_app_type] => B1 [patent_app_number] => 10/026671 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559707.pdf [firstpage_image] =>[orig_patent_app_number] => 10026671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026671
Bootstrap circuit Dec 26, 2001 Issued
Array ( [id] => 1406943 [patent_doc_number] => 06531899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Integrated differential current comparator with input to output electrical isolation' [patent_app_type] => B1 [patent_app_number] => 10/033565 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3328 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531899.pdf [firstpage_image] =>[orig_patent_app_number] => 10033565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033565
Integrated differential current comparator with input to output electrical isolation Dec 26, 2001 Issued
Array ( [id] => 1371506 [patent_doc_number] => 06570440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Direct-timed sneak current cancellation' [patent_app_type] => B1 [patent_app_number] => 10/035876 [patent_app_country] => US [patent_app_date] => 2001-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3039 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570440.pdf [firstpage_image] =>[orig_patent_app_number] => 10035876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035876
Direct-timed sneak current cancellation Dec 23, 2001 Issued
Array ( [id] => 5902009 [patent_doc_number] => 20020140498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Circuit generating a stable reference voltage with respect to temperature, particularly for CMOS processes' [patent_app_type] => new [patent_app_number] => 10/032231 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3783 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20020140498.pdf [firstpage_image] =>[orig_patent_app_number] => 10032231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032231
Circuit generating a stable reference voltage with respect to temperature, particularly for CMOS processes Dec 20, 2001 Issued
Array ( [id] => 1151853 [patent_doc_number] => 06774682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Circuit configuration for driving a semiconductor switching element and method for same' [patent_app_type] => B2 [patent_app_number] => 10/026241 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774682.pdf [firstpage_image] =>[orig_patent_app_number] => 10026241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026241
Circuit configuration for driving a semiconductor switching element and method for same Dec 20, 2001 Issued
Array ( [id] => 1413700 [patent_doc_number] => 06535054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Band-gap reference circuit with offset cancellation' [patent_app_type] => B1 [patent_app_number] => 10/032107 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535054.pdf [firstpage_image] =>[orig_patent_app_number] => 10032107 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032107
Band-gap reference circuit with offset cancellation Dec 19, 2001 Issued
Array ( [id] => 1410221 [patent_doc_number] => 06538493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 10/021059 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7910 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538493.pdf [firstpage_image] =>[orig_patent_app_number] => 10021059 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/021059
Semiconductor integrated circuit Dec 18, 2001 Issued
Array ( [id] => 1423400 [patent_doc_number] => 06522193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Internal voltage generator for semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 10/020576 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5076 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522193.pdf [firstpage_image] =>[orig_patent_app_number] => 10020576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020576
Internal voltage generator for semiconductor memory device Dec 17, 2001 Issued
10/022033 Charge pump circuit Dec 11, 2001 Abandoned
Array ( [id] => 1403463 [patent_doc_number] => 06545530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Circuit and method for reducing quiescent current in a voltage reference circuit' [patent_app_type] => B1 [patent_app_number] => 10/010398 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5503 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545530.pdf [firstpage_image] =>[orig_patent_app_number] => 10010398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010398
Circuit and method for reducing quiescent current in a voltage reference circuit Dec 4, 2001 Issued
Array ( [id] => 1498022 [patent_doc_number] => 06404275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Modified current mirror circuit for BiCMOS application' [patent_app_type] => B1 [patent_app_number] => 09/683193 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2969 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404275.pdf [firstpage_image] =>[orig_patent_app_number] => 09683193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683193
Modified current mirror circuit for BiCMOS application Nov 28, 2001 Issued
Array ( [id] => 6060951 [patent_doc_number] => 20020030535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Dynamic bias circuitry utilizing early voltage clamp and translinear techniques' [patent_app_type] => new [patent_app_number] => 09/989471 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5446 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030535.pdf [firstpage_image] =>[orig_patent_app_number] => 09989471 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989471
Dynamic bias circuitry utilizing early voltage clamp and translinear techniques Nov 18, 2001 Issued
Array ( [id] => 7643336 [patent_doc_number] => 06429706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Voltage sequencing circuit for powering-up sensitive electrical components' [patent_app_type] => B1 [patent_app_number] => 09/983423 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429706.pdf [firstpage_image] =>[orig_patent_app_number] => 09983423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/983423
Voltage sequencing circuit for powering-up sensitive electrical components Oct 23, 2001 Issued
Array ( [id] => 1583697 [patent_doc_number] => 06424199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Semiconductor device using complementary clock and signal input state detection circuit used for the same' [patent_app_type] => B1 [patent_app_number] => 09/978022 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 13625 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424199.pdf [firstpage_image] =>[orig_patent_app_number] => 09978022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978022
Semiconductor device using complementary clock and signal input state detection circuit used for the same Oct 16, 2001 Issued
Array ( [id] => 1426106 [patent_doc_number] => 06515530 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Dynamically scalable low voltage clock generation system' [patent_app_type] => B1 [patent_app_number] => 09/974985 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4474 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515530.pdf [firstpage_image] =>[orig_patent_app_number] => 09974985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974985
Dynamically scalable low voltage clock generation system Oct 10, 2001 Issued
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