
Jeffery Shawn Zweizig
Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2849, 2842, 2504 |
| Total Applications | 2640 |
| Issued Applications | 2460 |
| Pending Applications | 67 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1519582
[patent_doc_number] => 06501321
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[patent_kind] => B2
[patent_issue_date] => 2002-12-31
[patent_title] => 'Level shift circuit'
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[patent_app_number] => 09/971457
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Array
(
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[patent_issue_date] => 2003-11-18
[patent_title] => 'Dual-node capacitor coupled MOSFET for improving ESD performance'
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Array
(
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[patent_title] => 'Semiconductor controller device having a controlled output driver characteristic'
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Array
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[patent_title] => 'Power efficient line driver with 4X supply voltage swing and active termination'
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Array
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Array
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Array
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Array
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[patent_title] => 'Electrostatic discharge protection device for an integrated transistor'
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Array
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Array
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[patent_title] => 'Eliminating power-down popping in audio power amplifiers'
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Array
(
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Array
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Array
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Array
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