Search

Jeffery Shawn Zweizig

Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2849, 2842, 2504
Total Applications
2640
Issued Applications
2460
Pending Applications
67
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1519582 [patent_doc_number] => 06501321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Level shift circuit' [patent_app_type] => B2 [patent_app_number] => 09/971457 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6500 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501321.pdf [firstpage_image] =>[orig_patent_app_number] => 09971457 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971457
Level shift circuit Oct 4, 2001 Issued
Array ( [id] => 1265545 [patent_doc_number] => RE038319 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Dual-node capacitor coupled MOSFET for improving ESD performance' [patent_app_type] => E1 [patent_app_number] => 09/961341 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2622 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038319.pdf [firstpage_image] =>[orig_patent_app_number] => 09961341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961341
Dual-node capacitor coupled MOSFET for improving ESD performance Sep 24, 2001 Issued
Array ( [id] => 1389623 [patent_doc_number] => 06556052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Semiconductor controller device having a controlled output driver characteristic' [patent_app_type] => B2 [patent_app_number] => 09/954561 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6324 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556052.pdf [firstpage_image] =>[orig_patent_app_number] => 09954561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954561
Semiconductor controller device having a controlled output driver characteristic Sep 11, 2001 Issued
Array ( [id] => 1410326 [patent_doc_number] => 06538500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Power efficient line driver with 4X supply voltage swing and active termination' [patent_app_type] => B2 [patent_app_number] => 09/938776 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 988 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538500.pdf [firstpage_image] =>[orig_patent_app_number] => 09938776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938776
Power efficient line driver with 4X supply voltage swing and active termination Aug 23, 2001 Issued
Array ( [id] => 1425764 [patent_doc_number] => 06507231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Programmable clamp for output circuit' [patent_app_type] => B1 [patent_app_number] => 09/939201 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507231.pdf [firstpage_image] =>[orig_patent_app_number] => 09939201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939201
Programmable clamp for output circuit Aug 23, 2001 Issued
Array ( [id] => 5918732 [patent_doc_number] => 20020113643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Circuit for the filtering of parasitic logic signals' [patent_app_type] => new [patent_app_number] => 09/938289 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4747 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113643.pdf [firstpage_image] =>[orig_patent_app_number] => 09938289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938289
Circuit for the filtering of parasitic logic signals Aug 22, 2001 Issued
Array ( [id] => 1421675 [patent_doc_number] => 06525593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method and apparatus for local and global power management in a programmable analog circuit' [patent_app_type] => B1 [patent_app_number] => 09/935454 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525593.pdf [firstpage_image] =>[orig_patent_app_number] => 09935454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935454
Method and apparatus for local and global power management in a programmable analog circuit Aug 21, 2001 Issued
Array ( [id] => 6285771 [patent_doc_number] => 20020053934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Electrostatic discharge protection device for an integrated transistor' [patent_app_type] => new [patent_app_number] => 09/934452 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053934.pdf [firstpage_image] =>[orig_patent_app_number] => 09934452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934452
Electrostatic discharge protection device for an integrated transistor Aug 20, 2001 Issued
Array ( [id] => 6206027 [patent_doc_number] => 20020070794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'High efficiency electronic circuit for generating and regulating a supply voltage' [patent_app_type] => new [patent_app_number] => 09/935056 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3127 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070794.pdf [firstpage_image] =>[orig_patent_app_number] => 09935056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935056
High efficiency electronic circuit for generating and regulating a supply voltage Aug 20, 2001 Issued
Array ( [id] => 6462078 [patent_doc_number] => 20020021164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Eliminating power-down popping in audio power amplifiers' [patent_app_type] => new [patent_app_number] => 09/932318 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 468 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021164.pdf [firstpage_image] =>[orig_patent_app_number] => 09932318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932318
Eliminating power-down popping in audio power amplifiers Aug 16, 2001 Issued
Array ( [id] => 1383151 [patent_doc_number] => 06563367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Interconnection switch structures' [patent_app_type] => B1 [patent_app_number] => 09/930863 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2963 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563367.pdf [firstpage_image] =>[orig_patent_app_number] => 09930863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930863
Interconnection switch structures Aug 15, 2001 Issued
Array ( [id] => 1403153 [patent_doc_number] => 06545512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Low leakage sleep mode for dynamic circuits' [patent_app_type] => B2 [patent_app_number] => 09/931303 [patent_app_country] => US [patent_app_date] => 2001-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2429 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545512.pdf [firstpage_image] =>[orig_patent_app_number] => 09931303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931303
Low leakage sleep mode for dynamic circuits Aug 15, 2001 Issued
Array ( [id] => 1429917 [patent_doc_number] => 06504417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Active trim circuit for CMOS on-chip resistors' [patent_app_type] => B1 [patent_app_number] => 09/930670 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1768 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504417.pdf [firstpage_image] =>[orig_patent_app_number] => 09930670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930670
Active trim circuit for CMOS on-chip resistors Aug 14, 2001 Issued
Array ( [id] => 1407281 [patent_doc_number] => 06542026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Apparatus for on-chip reference voltage generator for receivers in high speed single-ended data link' [patent_app_type] => B2 [patent_app_number] => 09/931696 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542026.pdf [firstpage_image] =>[orig_patent_app_number] => 09931696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/931696
Apparatus for on-chip reference voltage generator for receivers in high speed single-ended data link Aug 14, 2001 Issued
Array ( [id] => 6837486 [patent_doc_number] => 20030034826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Voltage charge pump with circuit to prevent pass device latch-up' [patent_app_type] => new [patent_app_number] => 09/929776 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8543 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 53 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034826.pdf [firstpage_image] =>[orig_patent_app_number] => 09929776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929776
Voltage charge pump with circuit to prevent pass device latch-up Aug 13, 2001 Issued
Array ( [id] => 1429911 [patent_doc_number] => 06504416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'High linearity, low power voltage controlled resistor' [patent_app_type] => B1 [patent_app_number] => 09/929195 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504416.pdf [firstpage_image] =>[orig_patent_app_number] => 09929195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929195
High linearity, low power voltage controlled resistor Aug 13, 2001 Issued
Array ( [id] => 1519600 [patent_doc_number] => 06501328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method for reducing peak to peak jitter in a dual-loop delay locked loop' [patent_app_type] => B1 [patent_app_number] => 09/930435 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1434 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501328.pdf [firstpage_image] =>[orig_patent_app_number] => 09930435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930435
Method for reducing peak to peak jitter in a dual-loop delay locked loop Aug 13, 2001 Issued
Array ( [id] => 6237449 [patent_doc_number] => 20020043669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/927371 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3706 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043669.pdf [firstpage_image] =>[orig_patent_app_number] => 09927371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927371
Semiconductor device Aug 12, 2001 Issued
Array ( [id] => 6686753 [patent_doc_number] => 20030030476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'CURRENT SAVING MODE FOR INPUT BUFFERS' [patent_app_type] => new [patent_app_number] => 09/927587 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5699 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20030030476.pdf [firstpage_image] =>[orig_patent_app_number] => 09927587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927587
Current saving mode for input buffers Aug 9, 2001 Issued
Array ( [id] => 1481547 [patent_doc_number] => 06452443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Stable, low-noise bimodal audio filter circuit' [patent_app_type] => B1 [patent_app_number] => 09/925075 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1871 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452443.pdf [firstpage_image] =>[orig_patent_app_number] => 09925075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925075
Stable, low-noise bimodal audio filter circuit Aug 7, 2001 Issued
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