
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1406943
[patent_doc_number] => 06531899
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Integrated differential current comparator with input to output electrical isolation'
[patent_app_type] => B1
[patent_app_number] => 10/033565
[patent_app_country] => US
[patent_app_date] => 2001-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3328
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/531/06531899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10033565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/033565 | Integrated differential current comparator with input to output electrical isolation | Dec 26, 2001 | Issued |
Array
(
[id] => 1387805
[patent_doc_number] => 06559707
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-06
[patent_title] => 'Bootstrap circuit'
[patent_app_type] => B1
[patent_app_number] => 10/026671
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026671 | Bootstrap circuit | Dec 26, 2001 | Issued |
Array
(
[id] => 1371506
[patent_doc_number] => 06570440
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[patent_kind] => B1
[patent_issue_date] => 2003-05-27
[patent_title] => 'Direct-timed sneak current cancellation'
[patent_app_type] => B1
[patent_app_number] => 10/035876
[patent_app_country] => US
[patent_app_date] => 2001-12-24
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[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 10035876
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/035876 | Direct-timed sneak current cancellation | Dec 23, 2001 | Issued |
Array
(
[id] => 1151853
[patent_doc_number] => 06774682
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Circuit configuration for driving a semiconductor switching element and method for same'
[patent_app_type] => B2
[patent_app_number] => 10/026241
[patent_app_country] => US
[patent_app_date] => 2001-12-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/774/06774682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10026241
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/026241 | Circuit configuration for driving a semiconductor switching element and method for same | Dec 20, 2001 | Issued |
Array
(
[id] => 5902009
[patent_doc_number] => 20020140498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Circuit generating a stable reference voltage with respect to temperature, particularly for CMOS processes'
[patent_app_type] => new
[patent_app_number] => 10/032231
[patent_app_country] => US
[patent_app_date] => 2001-12-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/032231 | Circuit generating a stable reference voltage with respect to temperature, particularly for CMOS processes | Dec 20, 2001 | Issued |
Array
(
[id] => 1413700
[patent_doc_number] => 06535054
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Band-gap reference circuit with offset cancellation'
[patent_app_type] => B1
[patent_app_number] => 10/032107
[patent_app_country] => US
[patent_app_date] => 2001-12-20
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[pdf_file] => patents/06/535/06535054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10032107
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/032107 | Band-gap reference circuit with offset cancellation | Dec 19, 2001 | Issued |
Array
(
[id] => 1410221
[patent_doc_number] => 06538493
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-25
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => B2
[patent_app_number] => 10/021059
[patent_app_country] => US
[patent_app_date] => 2001-12-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/538/06538493.pdf
[firstpage_image] =>[orig_patent_app_number] => 10021059
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/021059 | Semiconductor integrated circuit | Dec 18, 2001 | Issued |
Array
(
[id] => 1423400
[patent_doc_number] => 06522193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-18
[patent_title] => 'Internal voltage generator for semiconductor memory device'
[patent_app_type] => B2
[patent_app_number] => 10/020576
[patent_app_country] => US
[patent_app_date] => 2001-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/06/522/06522193.pdf
[firstpage_image] =>[orig_patent_app_number] => 10020576
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/020576 | Internal voltage generator for semiconductor memory device | Dec 17, 2001 | Issued |
| 10/022033 | Charge pump circuit | Dec 11, 2001 | Abandoned |
Array
(
[id] => 1403463
[patent_doc_number] => 06545530
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-08
[patent_title] => 'Circuit and method for reducing quiescent current in a voltage reference circuit'
[patent_app_type] => B1
[patent_app_number] => 10/010398
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[firstpage_image] =>[orig_patent_app_number] => 10010398
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/010398 | Circuit and method for reducing quiescent current in a voltage reference circuit | Dec 4, 2001 | Issued |
Array
(
[id] => 1498022
[patent_doc_number] => 06404275
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Modified current mirror circuit for BiCMOS application'
[patent_app_type] => B1
[patent_app_number] => 09/683193
[patent_app_country] => US
[patent_app_date] => 2001-11-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/404/06404275.pdf
[firstpage_image] =>[orig_patent_app_number] => 09683193
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/683193 | Modified current mirror circuit for BiCMOS application | Nov 28, 2001 | Issued |
Array
(
[id] => 6060951
[patent_doc_number] => 20020030535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-14
[patent_title] => 'Dynamic bias circuitry utilizing early voltage clamp and translinear techniques'
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[patent_app_number] => 09/989471
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[pdf_file] => publications/A1/0030/20020030535.pdf
[firstpage_image] =>[orig_patent_app_number] => 09989471
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/989471 | Dynamic bias circuitry utilizing early voltage clamp and translinear techniques | Nov 18, 2001 | Issued |
Array
(
[id] => 7643336
[patent_doc_number] => 06429706
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[patent_title] => 'Voltage sequencing circuit for powering-up sensitive electrical components'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/983423 | Voltage sequencing circuit for powering-up sensitive electrical components | Oct 23, 2001 | Issued |
Array
(
[id] => 1583697
[patent_doc_number] => 06424199
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[patent_title] => 'Semiconductor device using complementary clock and signal input state detection circuit used for the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/978022 | Semiconductor device using complementary clock and signal input state detection circuit used for the same | Oct 16, 2001 | Issued |
Array
(
[id] => 1426106
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[patent_title] => 'Dynamically scalable low voltage clock generation system'
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[firstpage_image] =>[orig_patent_app_number] => 09974985
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/974985 | Dynamically scalable low voltage clock generation system | Oct 10, 2001 | Issued |
Array
(
[id] => 1519582
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[patent_title] => 'Level shift circuit'
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Array
(
[id] => 1265545
[patent_doc_number] => RE038319
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[patent_issue_date] => 2003-11-18
[patent_title] => 'Dual-node capacitor coupled MOSFET for improving ESD performance'
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[patent_app_number] => 09/961341
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[firstpage_image] =>[orig_patent_app_number] => 09961341
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/961341 | Dual-node capacitor coupled MOSFET for improving ESD performance | Sep 24, 2001 | Issued |
Array
(
[id] => 1389623
[patent_doc_number] => 06556052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-04-29
[patent_title] => 'Semiconductor controller device having a controlled output driver characteristic'
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[firstpage_image] =>[orig_patent_app_number] => 09954561
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/954561 | Semiconductor controller device having a controlled output driver characteristic | Sep 11, 2001 | Issued |
Array
(
[id] => 1410326
[patent_doc_number] => 06538500
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[patent_title] => 'Power efficient line driver with 4X supply voltage swing and active termination'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/938776 | Power efficient line driver with 4X supply voltage swing and active termination | Aug 23, 2001 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/939201 | Programmable clamp for output circuit | Aug 23, 2001 | Issued |