Search

Jeffrey David Asch

Examiner (ID: 17973, Phone: (571)272-2632 , Office: P/2916 )

Most Active Art Unit
2913
Art Unit(s)
2916, 2900, 2913, OPQA, 2903
Total Applications
7336
Issued Applications
7271
Pending Applications
1
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18229500 [patent_doc_number] => 20230068494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Multi-Activation Techniques for Partial Write Operations [patent_app_type] => utility [patent_app_number] => 17/410657 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410657 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410657
Multi-activation techniques for partial write operations Aug 23, 2021 Issued
Array ( [id] => 17415729 [patent_doc_number] => 20220050633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => PRE-EMPTIVE STORAGE STRATEGIES TO REDUCE HOST COMMAND COLLISIONS [patent_app_type] => utility [patent_app_number] => 17/389856 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389856
Pre-emptive storage strategies to reduce host command collisions Jul 29, 2021 Issued
Array ( [id] => 19459256 [patent_doc_number] => 12099748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => NAND temperature-aware operations [patent_app_type] => utility [patent_app_number] => 17/373301 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 14271 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373301
NAND temperature-aware operations Jul 11, 2021 Issued
Array ( [id] => 18584614 [patent_doc_number] => 20230266878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METADATA VOLUME BITMAP DATA CONFLICT PROCESSING METHOD AND RELATED COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/012933 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18012933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/012933
Metadata volume bitmap data conflict processing method and related components Jun 29, 2021 Issued
Array ( [id] => 18622206 [patent_doc_number] => 11755246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Efficient rank switching in multi-rank memory controller [patent_app_type] => utility [patent_app_number] => 17/357007 [patent_app_country] => US [patent_app_date] => 2021-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17357007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/357007
Efficient rank switching in multi-rank memory controller Jun 23, 2021 Issued
Array ( [id] => 17832122 [patent_doc_number] => 20220269426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => RESOURCE ALLOCATION IN A STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/304241 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304241
Resource allocation in a storage system Jun 15, 2021 Issued
Array ( [id] => 17475769 [patent_doc_number] => 20220083273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/344230 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -42 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344230
Memory system with write modes based on an internal state of a memory controller Jun 9, 2021 Issued
Array ( [id] => 18430321 [patent_doc_number] => 11675539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => File system operations for a storage supporting a plurality of submission queues [patent_app_type] => utility [patent_app_number] => 17/338507 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5830 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338507
File system operations for a storage supporting a plurality of submission queues Jun 2, 2021 Issued
Array ( [id] => 18668316 [patent_doc_number] => 11775214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory system for suspending and resuming execution of command according to lock or unlock request, and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/338246 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10290 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338246
Memory system for suspending and resuming execution of command according to lock or unlock request, and operating method thereof Jun 2, 2021 Issued
Array ( [id] => 16994088 [patent_doc_number] => 20210232508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => LAST WRITTEN PAGE SEARCHING [patent_app_type] => utility [patent_app_number] => 17/227473 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227473
LAST WRITTEN PAGE SEARCHING Apr 11, 2021 Abandoned
Array ( [id] => 17915527 [patent_doc_number] => 20220317923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => WRITE BANK GROUP MASK DURING ARBITRATION [patent_app_type] => utility [patent_app_number] => 17/218676 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218676
Write bank group mask during arbitration Mar 30, 2021 Issued
Array ( [id] => 18189225 [patent_doc_number] => 11579810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor memory training method and related device [patent_app_type] => utility [patent_app_number] => 17/434105 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 14622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17434105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/434105
Semiconductor memory training method and related device Mar 8, 2021 Issued
Array ( [id] => 17629126 [patent_doc_number] => 20220164141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => Memory Controller Utilizing Sets of Access Settings Corresponding to Memory Dies, and Control Method thereof [patent_app_type] => utility [patent_app_number] => 17/194298 [patent_app_country] => US [patent_app_date] => 2021-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194298
Memory Controller Utilizing Sets of Access Settings Corresponding to Memory Dies, and Control Method thereof Mar 6, 2021 Abandoned
Array ( [id] => 19419999 [patent_doc_number] => 20240296122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SYSTEMS AND METHODS FOR CACHING METADATA [patent_app_type] => utility [patent_app_number] => 17/908879 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17908879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/908879
Systems and methods for caching metadata Mar 2, 2021 Issued
Array ( [id] => 18454072 [patent_doc_number] => 20230195352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD FOR DILUTING CACHE SPACE, AND DEVICE AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/928150 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17928150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/928150
Method for diluting cache space, and device and medium Feb 18, 2021 Issued
Array ( [id] => 17706704 [patent_doc_number] => 20220206710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => NONVOLATILE MEMORY WITH ENCODING FOR FOGGY-FINE PROGRAMMING WITH SOFT BITS [patent_app_type] => utility [patent_app_number] => 17/171599 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171599
Nonvolatile memory with encoding for foggy-fine programming with soft bits Feb 8, 2021 Issued
Array ( [id] => 17415727 [patent_doc_number] => 20220050631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => TIMING DETECTION CIRCUIT, SEMICONDUCTOR DEVICE, AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/168692 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168692
Timing detection circuit, semiconductor device, and memory system having delay elements in matrix Feb 4, 2021 Issued
Array ( [id] => 18703138 [patent_doc_number] => 11789648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method and apparatus and computer program product for configuring reliable command [patent_app_type] => utility [patent_app_number] => 17/169139 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4750 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169139
Method and apparatus and computer program product for configuring reliable command Feb 4, 2021 Issued
Array ( [id] => 18686902 [patent_doc_number] => 11782638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Storage device with improved read latency and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/160059 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160059
Storage device with improved read latency and operating method thereof Jan 26, 2021 Issued
Array ( [id] => 17999456 [patent_doc_number] => 11500563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Memory system and operating method for testing target firmware by processing a plurality of test commands [patent_app_type] => utility [patent_app_number] => 17/151551 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10681 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151551
Memory system and operating method for testing target firmware by processing a plurality of test commands Jan 17, 2021 Issued
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