Search

Jeffrey David Asch

Examiner (ID: 17973, Phone: (571)272-2632 , Office: P/2916 )

Most Active Art Unit
2913
Art Unit(s)
2916, 2900, 2913, OPQA, 2903
Total Applications
7336
Issued Applications
7271
Pending Applications
1
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17157764 [patent_doc_number] => 20210318815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR SUPPORTING MULTIPLE CONNECTORS ON STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 16/926636 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926636
Systems, methods, and apparatus for supporting multiple connectors on storage devices Jul 9, 2020 Issued
Array ( [id] => 17423173 [patent_doc_number] => 11256627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Directly mapped buffer cache on non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/907703 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/907703
Directly mapped buffer cache on non-volatile memory Jun 21, 2020 Issued
Array ( [id] => 17262379 [patent_doc_number] => 20210375364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => ADJUSTMENT OF A STARTING VOLTAGE CORRESPONDING TO A PROGRAM OPERATION IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 16/885977 [patent_app_country] => US [patent_app_date] => 2020-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885977 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885977
Adjustment of a starting voltage corresponding to a program operation in a memory sub-system May 27, 2020 Issued
Array ( [id] => 17245466 [patent_doc_number] => 20210365209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => SYSTEM AND METHOD FOR REGULATING NVMe-oF COMMAND REQUESTS AND DATA FLOW ACROSS A NETWORK WITH MISMATCHED RATES [patent_app_type] => utility [patent_app_number] => 16/878444 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878444 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878444
System and method for regulating NVMe-oF command requests and data flow across a network with mismatched rates May 18, 2020 Issued
Array ( [id] => 17216323 [patent_doc_number] => 20210349661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => ASYNCHRONOUS PROCESS TOPOLOGY IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/866740 [patent_app_country] => US [patent_app_date] => 2020-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/866740
Asynchronous process topology in a memory device May 4, 2020 Issued
Array ( [id] => 16729613 [patent_doc_number] => 20210096760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => APPARATUS AND METHOD FOR TRANSCEIVING OPERATION INFORMATION IN A DATA PROCESSING SYSTEM INCLUDING A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/856123 [patent_app_country] => US [patent_app_date] => 2020-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16856123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/856123
APPARATUS AND METHOD FOR TRANSCEIVING OPERATION INFORMATION IN A DATA PROCESSING SYSTEM INCLUDING A MEMORY SYSTEM Apr 22, 2020 Abandoned
Array ( [id] => 17698821 [patent_doc_number] => 11372543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Zone-append command scheduling based on zone state [patent_app_type] => utility [patent_app_number] => 16/845685 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8300 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845685
Zone-append command scheduling based on zone state Apr 9, 2020 Issued
Array ( [id] => 17824341 [patent_doc_number] => 11429289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Memory map protection mechanism [patent_app_type] => utility [patent_app_number] => 16/832125 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832125
Memory map protection mechanism Mar 26, 2020 Issued
Array ( [id] => 17565205 [patent_doc_number] => 20220129354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => BACKUP RESTORATION METHOD AND BACKUP RESTORATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/427169 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/427169
Backup restoration method and backup restoration device Jan 16, 2020 Issued
Array ( [id] => 15836485 [patent_doc_number] => 20200133525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SYSTEMS AND METHODS FOR DATA PATH POWER SAVINGS IN DDR5 MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/730792 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730792 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730792
Systems and methods for data path power savings in DDR5 memory devices Dec 29, 2019 Issued
Array ( [id] => 18547000 [patent_doc_number] => 11720352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Flexible command pointers to microcode operations [patent_app_type] => utility [patent_app_number] => 16/708971 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6157 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/708971
Flexible command pointers to microcode operations Dec 9, 2019 Issued
Array ( [id] => 16675482 [patent_doc_number] => 20210064248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SCANNING TECHNIQUES FOR A MEDIA-MANAGEMENT OPERATION OF A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 16/555997 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555997
Scanning techniques for a media-management operation of a memory sub-system Aug 28, 2019 Issued
Array ( [id] => 18370622 [patent_doc_number] => 11650795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Raw read based physically unclonable function for flash memory [patent_app_type] => utility [patent_app_number] => 16/549621 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5730 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549621
Raw read based physically unclonable function for flash memory Aug 22, 2019 Issued
Array ( [id] => 17706689 [patent_doc_number] => 20220206695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DYNAMIC CHANNEL MAPPING FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/982483 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/982483
Dynamic channel mapping for a memory system Aug 22, 2019 Issued
Array ( [id] => 17824470 [patent_doc_number] => 11429418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Asynchronous input and output for snapshots of virtual machines [patent_app_type] => utility [patent_app_number] => 16/527470 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15093 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527470
Asynchronous input and output for snapshots of virtual machines Jul 30, 2019 Issued
Array ( [id] => 16486301 [patent_doc_number] => 20200379907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => REDUCING CACHE INTERFERENCE BASED ON FORECASTED PROCESSOR USE [patent_app_type] => utility [patent_app_number] => 16/510756 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510756 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510756
Reducing cache interference based on forecasted processor use Jul 11, 2019 Issued
Array ( [id] => 16818544 [patent_doc_number] => 11003370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => System on chip performing a plurality of trainings at the same time, operating method of system on chip, electronic device including system on chip [patent_app_type] => utility [patent_app_number] => 16/457164 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457164 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457164
System on chip performing a plurality of trainings at the same time, operating method of system on chip, electronic device including system on chip Jun 27, 2019 Issued
Array ( [id] => 16543386 [patent_doc_number] => 20200409801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => STREAM LEVEL UNINTERRUPTED RESTORE OPERATION USING DATA PROBE [patent_app_type] => utility [patent_app_number] => 16/453674 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453674 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453674
Stream level uninterrupted restore operation using data probe Jun 25, 2019 Issued
Array ( [id] => 17365790 [patent_doc_number] => 11232818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => Memory system performing reference voltage training operation and operating method of memory system [patent_app_type] => utility [patent_app_number] => 16/265736 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5492 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/265736
Memory system performing reference voltage training operation and operating method of memory system Jan 31, 2019 Issued
Array ( [id] => 15773191 [patent_doc_number] => 20200117613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Configuration Cache For The ARM SMMUv3 [patent_app_type] => utility [patent_app_number] => 16/158443 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/158443
Configuration cache for the ARM SMMUv3 Oct 11, 2018 Issued
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