Search

Jeffrey Donels

Examiner (ID: 8246, Phone: (571)272-2061 , Office: P/2837 )

Most Active Art Unit
2837
Art Unit(s)
2832, 3621, 2837, 2107
Total Applications
2703
Issued Applications
2321
Pending Applications
127
Abandoned Applications
255

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16264660 [patent_doc_number] => 10756107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Semiconductor device including partially enlarged channel hole [patent_app_type] => utility [patent_app_number] => 16/203790 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 7826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203790 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203790
Semiconductor device including partially enlarged channel hole Nov 28, 2018 Issued
Array ( [id] => 16339304 [patent_doc_number] => 10790273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Integrated circuits including standard cells and method of manufacturing the integrated circuits [patent_app_type] => utility [patent_app_number] => 16/203845 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 11298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203845
Integrated circuits including standard cells and method of manufacturing the integrated circuits Nov 28, 2018 Issued
Array ( [id] => 16000979 [patent_doc_number] => 20200176360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => LOW INDUCTANCE STACKABLE SOLID-STATE SWITCHING MODULE AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 16/203777 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203777
Low inductance stackable solid-state switching module and method of manufacturing thereof Nov 28, 2018 Issued
Array ( [id] => 16000775 [patent_doc_number] => 20200176258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION [patent_app_type] => utility [patent_app_number] => 16/203816 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203816 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203816
Late gate cut using selective conductor deposition Nov 28, 2018 Issued
Array ( [id] => 16707719 [patent_doc_number] => 10957663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Spoked solder pad to improve solderability and self-alignment of integrated circuit packages [patent_app_type] => utility [patent_app_number] => 16/197221 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197221
Spoked solder pad to improve solderability and self-alignment of integrated circuit packages Nov 19, 2018 Issued
Array ( [id] => 14049931 [patent_doc_number] => 20190081073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/189625 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189625
Semiconductor memory device Nov 12, 2018 Issued
Array ( [id] => 14050069 [patent_doc_number] => 20190081142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Power Semiconductor Device Having Cells with Channel Regions of Different Conductivity Types [patent_app_type] => utility [patent_app_number] => 16/189858 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16189858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/189858
Power semiconductor device having cells with channel regions of different conductivity types Nov 12, 2018 Issued
Array ( [id] => 15424877 [patent_doc_number] => 10545364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Matrix circuit substrate, display apparatus, and manufacturing method of matrix circuit substrate [patent_app_type] => utility [patent_app_number] => 16/184040 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8416 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184040
Matrix circuit substrate, display apparatus, and manufacturing method of matrix circuit substrate Nov 7, 2018 Issued
Array ( [id] => 17224901 [patent_doc_number] => 11177411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Photosensitive field-effect transistor [patent_app_type] => utility [patent_app_number] => 16/758736 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4709 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16758736 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/758736
Photosensitive field-effect transistor Oct 22, 2018 Issued
Array ( [id] => 15808103 [patent_doc_number] => 20200127194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => EMBEDDED MAGNETIC TUNNEL JUNCTION PILLAR HAVING REDUCED HEIGHT AND UNIFORM CONTACT AREA [patent_app_type] => utility [patent_app_number] => 16/165352 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165352
Embedded magnetic tunnel junction pillar having reduced height and uniform contact area Oct 18, 2018 Issued
Array ( [id] => 15955563 [patent_doc_number] => 10665698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface [patent_app_type] => utility [patent_app_number] => 16/165440 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 9643 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165440
Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface Oct 18, 2018 Issued
Array ( [id] => 16593909 [patent_doc_number] => 10903186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Power electronic assemblies with solder layer and exterior coating, and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/165563 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5263 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165563
Power electronic assemblies with solder layer and exterior coating, and methods of forming the same Oct 18, 2018 Issued
Array ( [id] => 14221665 [patent_doc_number] => 20190123217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Microlens Having a Carrier-Free Optical Interference Filter [patent_app_type] => utility [patent_app_number] => 16/165556 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165556
Microlens having a carrier-free optical interference filter Oct 18, 2018 Issued
Array ( [id] => 15611611 [patent_doc_number] => 10586877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/165414 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4386 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165414
Semiconductor device and method of manufacturing the same Oct 18, 2018 Issued
Array ( [id] => 15807297 [patent_doc_number] => 20200126791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => HARDMASK STRESS, GRAIN, AND STRUCTURE ENGINEERING FOR ADVANCED MEMORY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/165311 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165311
Hardmask stress, grain, and structure engineering for advanced memory applications Oct 18, 2018 Issued
Array ( [id] => 16047973 [patent_doc_number] => 10685869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/165525 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165525 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165525
Semiconductor device and method of forming the same Oct 18, 2018 Issued
Array ( [id] => 14164153 [patent_doc_number] => 20190109179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => Solid State Tissue Equivalent Detector With Gate Electrodes [patent_app_type] => utility [patent_app_number] => 16/156568 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16156568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/156568
Solid state tissue equivalent detector with gate electrodes Oct 9, 2018 Issued
Array ( [id] => 13909363 [patent_doc_number] => 20190043886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/149249 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149249
Memory device Oct 1, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
Array ( [id] => 16464282 [patent_doc_number] => 10847645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Transistor structures having a deep recessed P+ junction and methods for making same [patent_app_type] => utility [patent_app_number] => 16/148214 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7934 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148214
Transistor structures having a deep recessed P+ junction and methods for making same Sep 30, 2018 Issued
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