Search

Jeffrey Donels

Examiner (ID: 16730, Phone: (571)272-2061 , Office: P/2837 )

Most Active Art Unit
2837
Art Unit(s)
3621, 2837, 2107, 2832
Total Applications
2774
Issued Applications
2407
Pending Applications
133
Abandoned Applications
267

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1325164 [patent_doc_number] => 06615316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Using hardware counters to estimate cache warmth for process/thread schedulers' [patent_app_type] => B1 [patent_app_number] => 09/715444 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5421 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615316.pdf [firstpage_image] =>[orig_patent_app_number] => 09715444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715444
Using hardware counters to estimate cache warmth for process/thread schedulers Nov 15, 2000 Issued
Array ( [id] => 1416830 [patent_doc_number] => 06532514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'System and method for handling a power supply interruption in a non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/713564 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3200 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532514.pdf [firstpage_image] =>[orig_patent_app_number] => 09713564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713564
System and method for handling a power supply interruption in a non-volatile memory Nov 14, 2000 Issued
Array ( [id] => 7622361 [patent_doc_number] => 06687805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method and system for logical-object-to-physical-location translation and physical separation of logical objects' [patent_app_type] => B1 [patent_app_number] => 09/699596 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11299 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687805.pdf [firstpage_image] =>[orig_patent_app_number] => 09699596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699596
Method and system for logical-object-to-physical-location translation and physical separation of logical objects Oct 29, 2000 Issued
Array ( [id] => 1430970 [patent_doc_number] => 06507883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Recalling logical volumes to cache from physical media volumes for redundant storage in automated data storage libraries' [patent_app_type] => B1 [patent_app_number] => 09/693952 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6174 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507883.pdf [firstpage_image] =>[orig_patent_app_number] => 09693952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/693952
Recalling logical volumes to cache from physical media volumes for redundant storage in automated data storage libraries Oct 22, 2000 Issued
Array ( [id] => 1395690 [patent_doc_number] => 06567907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Avoiding mapping conflicts in a translation look-aside buffer' [patent_app_type] => B1 [patent_app_number] => 09/691973 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2521 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567907.pdf [firstpage_image] =>[orig_patent_app_number] => 09691973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691973
Avoiding mapping conflicts in a translation look-aside buffer Oct 18, 2000 Issued
Array ( [id] => 789406 [patent_doc_number] => 06988178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Emulation processing method for a storage device and storage device' [patent_app_type] => utility [patent_app_number] => 09/676447 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5482 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988178.pdf [firstpage_image] =>[orig_patent_app_number] => 09676447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676447
Emulation processing method for a storage device and storage device Sep 28, 2000 Issued
Array ( [id] => 1411471 [patent_doc_number] => 06553455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method and apparatus for providing passed pointer detection in audio/video streams on disk media' [patent_app_type] => B1 [patent_app_number] => 09/670482 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 6002 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553455.pdf [firstpage_image] =>[orig_patent_app_number] => 09670482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670482
Method and apparatus for providing passed pointer detection in audio/video streams on disk media Sep 25, 2000 Issued
Array ( [id] => 7623835 [patent_doc_number] => 06725342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Non-volatile mass storage cache coherency apparatus' [patent_app_type] => B1 [patent_app_number] => 09/669770 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6652 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725342.pdf [firstpage_image] =>[orig_patent_app_number] => 09669770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669770
Non-volatile mass storage cache coherency apparatus Sep 25, 2000 Issued
Array ( [id] => 7645901 [patent_doc_number] => 06477622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Simplified writeback handling' [patent_app_type] => B1 [patent_app_number] => 09/670856 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477622.pdf [firstpage_image] =>[orig_patent_app_number] => 09670856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670856
Simplified writeback handling Sep 25, 2000 Issued
Array ( [id] => 1225532 [patent_doc_number] => 06704835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Posted write-through cache for flash memory' [patent_app_type] => B1 [patent_app_number] => 09/669609 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4190 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704835.pdf [firstpage_image] =>[orig_patent_app_number] => 09669609 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669609
Posted write-through cache for flash memory Sep 25, 2000 Issued
Array ( [id] => 1240859 [patent_doc_number] => 06691215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method and apparatus for reducing power consumption' [patent_app_type] => B1 [patent_app_number] => 09/670418 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 15400 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691215.pdf [firstpage_image] =>[orig_patent_app_number] => 09670418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670418
Method and apparatus for reducing power consumption Sep 25, 2000 Issued
Array ( [id] => 1505987 [patent_doc_number] => 06487641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Dynamic caches with miss tables' [patent_app_type] => B1 [patent_app_number] => 09/654653 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487641.pdf [firstpage_image] =>[orig_patent_app_number] => 09654653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654653
Dynamic caches with miss tables Sep 4, 2000 Issued
Array ( [id] => 1243150 [patent_doc_number] => 06684316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Storage access unit for selective access to a static storage unit or dynamic storage unit and associated access procedures' [patent_app_type] => B1 [patent_app_number] => 09/651516 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4980 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684316.pdf [firstpage_image] =>[orig_patent_app_number] => 09651516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651516
Storage access unit for selective access to a static storage unit or dynamic storage unit and associated access procedures Aug 29, 2000 Issued
Array ( [id] => 1291793 [patent_doc_number] => 06643736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Scratch pad memories' [patent_app_type] => B1 [patent_app_number] => 09/650244 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1532 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643736.pdf [firstpage_image] =>[orig_patent_app_number] => 09650244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650244
Scratch pad memories Aug 28, 2000 Issued
Array ( [id] => 1062219 [patent_doc_number] => 06854034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Computer system and a method of assigning a storage device to a computer' [patent_app_type] => utility [patent_app_number] => 09/642817 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9722 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854034.pdf [firstpage_image] =>[orig_patent_app_number] => 09642817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642817
Computer system and a method of assigning a storage device to a computer Aug 21, 2000 Issued
Array ( [id] => 1120005 [patent_doc_number] => 06801985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses' [patent_app_type] => B1 [patent_app_number] => 09/637491 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7205 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801985.pdf [firstpage_image] =>[orig_patent_app_number] => 09637491 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637491
Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses Aug 10, 2000 Issued
Array ( [id] => 1381603 [patent_doc_number] => 06574710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Computer cache system with deferred invalidation' [patent_app_type] => B1 [patent_app_number] => 09/629128 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2833 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574710.pdf [firstpage_image] =>[orig_patent_app_number] => 09629128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629128
Computer cache system with deferred invalidation Jul 30, 2000 Issued
Array ( [id] => 1165663 [patent_doc_number] => 06772273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Block-level read while write method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/608454 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2505 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772273.pdf [firstpage_image] =>[orig_patent_app_number] => 09608454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608454
Block-level read while write method and apparatus Jun 28, 2000 Issued
Array ( [id] => 1134043 [patent_doc_number] => 06792500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Apparatus and method for managing memory defects' [patent_app_type] => B1 [patent_app_number] => 09/602473 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 37938 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792500.pdf [firstpage_image] =>[orig_patent_app_number] => 09602473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602473
Apparatus and method for managing memory defects Jun 22, 2000 Issued
Array ( [id] => 1314252 [patent_doc_number] => 06622197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Dynamic random access memory device capable of programming a refresh period and a bit organization' [patent_app_type] => B1 [patent_app_number] => 09/596836 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2536 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622197.pdf [firstpage_image] =>[orig_patent_app_number] => 09596836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596836
Dynamic random access memory device capable of programming a refresh period and a bit organization Jun 18, 2000 Issued
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