Search

Jeffrey Donels

Examiner (ID: 8246, Phone: (571)272-2061 , Office: P/2837 )

Most Active Art Unit
2837
Art Unit(s)
2832, 3621, 2837, 2107
Total Applications
2703
Issued Applications
2321
Pending Applications
127
Abandoned Applications
255

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13708967 [patent_doc_number] => 20170365438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => COMPACT MODULAR CATHODE [patent_app_type] => utility [patent_app_number] => 15/539384 [patent_app_country] => US [patent_app_date] => 2015-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15539384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/539384
Compact modular cathode Dec 22, 2015 Issued
Array ( [id] => 13242973 [patent_doc_number] => 10134696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Spoked solder pad to improve solderability and self-alignment of integrated circuit packages [patent_app_type] => utility [patent_app_number] => 14/977601 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4859 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977601
Spoked solder pad to improve solderability and self-alignment of integrated circuit packages Dec 20, 2015 Issued
Array ( [id] => 13257511 [patent_doc_number] => 10141453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/539541 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9607 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15539541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/539541
Semiconductor device Dec 14, 2015 Issued
Array ( [id] => 12154881 [patent_doc_number] => 20180026145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'LIGHT DETECTION DEVICE' [patent_app_type] => utility [patent_app_number] => 15/551099 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9360 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15551099 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/551099
Light detection device Dec 13, 2015 Issued
Array ( [id] => 11432757 [patent_doc_number] => 09571087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method of operating a reverse conducting IGBT' [patent_app_type] => utility [patent_app_number] => 14/963509 [patent_app_country] => US [patent_app_date] => 2015-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5460 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963509
Method of operating a reverse conducting IGBT Dec 8, 2015 Issued
Array ( [id] => 11751702 [patent_doc_number] => 09709710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Device including light blocking layer and method of patterning the light blocking layer' [patent_app_type] => utility [patent_app_number] => 14/940337 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7453 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14940337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/940337
Device including light blocking layer and method of patterning the light blocking layer Nov 12, 2015 Issued
Array ( [id] => 11898330 [patent_doc_number] => 09768272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity' [patent_app_type] => utility [patent_app_number] => 14/870936 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 8906 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14870936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/870936
Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity Sep 29, 2015 Issued
Array ( [id] => 11532640 [patent_doc_number] => 20170092618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'PACKAGE TOPSIDE BALL GRID ARRAY FOR ULTRA LOW Z-HEIGHT' [patent_app_type] => utility [patent_app_number] => 14/864616 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5145 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864616
PACKAGE TOPSIDE BALL GRID ARRAY FOR ULTRA LOW Z-HEIGHT Sep 23, 2015 Abandoned
Array ( [id] => 11532583 [patent_doc_number] => 20170092561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'THERMAL MANAGEMENT SOLUTIONS FOR MICROELECTRONIC DEVICES USING JUMPING DROPS VAPOR CHAMBERS' [patent_app_type] => utility [patent_app_number] => 14/863580 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5429 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863580 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/863580
THERMAL MANAGEMENT SOLUTIONS FOR MICROELECTRONIC DEVICES USING JUMPING DROPS VAPOR CHAMBERS Sep 23, 2015 Abandoned
Array ( [id] => 11532586 [patent_doc_number] => 20170092564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'THERMAL MANAGEMENT FOR FLEXIBLE INTEGRATED CIRCUIT PACKAGES' [patent_app_type] => utility [patent_app_number] => 14/864433 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15143 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864433
Thermal management for flexible integrated circuit packages Sep 23, 2015 Issued
Array ( [id] => 11539625 [patent_doc_number] => 09614044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Semiconductor device with current sensor' [patent_app_type] => utility [patent_app_number] => 14/853164 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853164 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853164
Semiconductor device with current sensor Sep 13, 2015 Issued
Array ( [id] => 11503116 [patent_doc_number] => 20170077301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'METHODS OF MAKING SOURCE/DRAIN REGIONS POSITIONED INSIDE U-SHAPED SEMICONDUCTOR MATERIAL USING SOURCE/DRAIN PLACEHOLDER STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/853073 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7400 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853073
Methods of making source/drain regions positioned inside U-shaped semiconductor material using source/drain placeholder structures Sep 13, 2015 Issued
Array ( [id] => 10802723 [patent_doc_number] => 20160148880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'ELECTRONIC DEVICE WITH STACKED CHIPS' [patent_app_type] => utility [patent_app_number] => 14/852711 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2601 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852711
Electronic device with stacked chips Sep 13, 2015 Issued
Array ( [id] => 11036341 [patent_doc_number] => 20160233297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'Semiconductor Device Having Shallow Trench Isolation Structure' [patent_app_type] => utility [patent_app_number] => 14/852852 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5214 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852852
Semiconductor device having shallow trench isolation structure Sep 13, 2015 Issued
Array ( [id] => 11279831 [patent_doc_number] => 09496314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area' [patent_app_type] => utility [patent_app_number] => 14/853116 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8380 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853116
Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area Sep 13, 2015 Issued
Array ( [id] => 11438291 [patent_doc_number] => 20170039311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR LAYOUT STRUCTURE AND DESIGNING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/852635 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11057 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852635 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852635
Semiconductor layout structure and designing method thereof Sep 13, 2015 Issued
Array ( [id] => 11502852 [patent_doc_number] => 20170077037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'VIA BOTTOM STRUCTURE AND METHODS OF FORMING' [patent_app_type] => utility [patent_app_number] => 14/853131 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3344 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853131
Via bottom structure and methods of forming Sep 13, 2015 Issued
Array ( [id] => 11503129 [patent_doc_number] => 20170077314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/853146 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8174 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853146 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853146
Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure Sep 13, 2015 Issued
Array ( [id] => 10733317 [patent_doc_number] => 20160079467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/852535 [patent_app_country] => US [patent_app_date] => 2015-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10158 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852535
Group III nitride semiconductor light-emitting device and production method therefor Sep 11, 2015 Issued
Array ( [id] => 10495509 [patent_doc_number] => 20150380531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN' [patent_app_type] => utility [patent_app_number] => 14/847743 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/847743
HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN Sep 7, 2015 Abandoned
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