Jeffrey Donels
Examiner (ID: 8246, Phone: (571)272-2061 , Office: P/2837 )
Most Active Art Unit | 2837 |
Art Unit(s) | 2832, 3621, 2837, 2107 |
Total Applications | 2703 |
Issued Applications | 2321 |
Pending Applications | 127 |
Abandoned Applications | 255 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10277321
[patent_doc_number] => 20150162318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'CHIP, CHIP PACKAGE AND DIE'
[patent_app_type] => utility
[patent_app_number] => 14/101370
[patent_app_country] => US
[patent_app_date] => 2013-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8699
[patent_no_of_claims] => 25
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101370
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101370 | Chip, chip package and die | Dec 9, 2013 | Issued |
Array
(
[id] => 11180821
[patent_doc_number] => 09412818
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-09
[patent_title] => 'System and method of manufacturing a fin field-effect transistor having multiple fin heights'
[patent_app_type] => utility
[patent_app_number] => 14/100489
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100489
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100489 | System and method of manufacturing a fin field-effect transistor having multiple fin heights | Dec 8, 2013 | Issued |
Array
(
[id] => 10277272
[patent_doc_number] => 20150162269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'SEMICONDUCTOR DIE PACKAGE WITH INSULATED WIRES FOR ROUTING POWER SIGNALS'
[patent_app_type] => utility
[patent_app_number] => 14/098560
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14098560
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/098560 | SEMICONDUCTOR DIE PACKAGE WITH INSULATED WIRES FOR ROUTING POWER SIGNALS | Dec 5, 2013 | Abandoned |
Array
(
[id] => 10277263
[patent_doc_number] => 20150162259
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'INTELLIGENT CHIP PLACEMENT WITHIN A THREE-DIMENSIONAL CHIP STACK'
[patent_app_type] => utility
[patent_app_number] => 14/097585
[patent_app_country] => US
[patent_app_date] => 2013-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 10623
[patent_no_of_claims] => 15
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097585
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/097585 | Intelligent chip placement within a three-dimensional chip stack | Dec 4, 2013 | Issued |
Array
(
[id] => 11564850
[patent_doc_number] => 09627445
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-18
[patent_title] => 'Optoelectronic component and a method for manufacturing an optoelectronic component'
[patent_app_type] => utility
[patent_app_number] => 14/097291
[patent_app_country] => US
[patent_app_date] => 2013-12-05
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/097291 | Optoelectronic component and a method for manufacturing an optoelectronic component | Dec 4, 2013 | Issued |
Array
(
[id] => 11411750
[patent_doc_number] => 09559064
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-31
[patent_title] => 'Warpage control in package-on-package structures'
[patent_app_type] => utility
[patent_app_number] => 14/096456
[patent_app_country] => US
[patent_app_date] => 2013-12-04
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/096456 | Warpage control in package-on-package structures | Dec 3, 2013 | Issued |
Array
(
[id] => 10270270
[patent_doc_number] => 20150155267
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-04
[patent_title] => 'Electronic component with sheet-like redistribution structure'
[patent_app_type] => utility
[patent_app_number] => 14/096063
[patent_app_country] => US
[patent_app_date] => 2013-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096063
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/096063 | Electronic component with sheet-like redistribution structure | Dec 3, 2013 | Issued |
Array
(
[id] => 11787588
[patent_doc_number] => 09397051
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-19
[patent_title] => 'Warpage reduction in structures with electrical circuitry'
[patent_app_type] => utility
[patent_app_number] => 14/095704
[patent_app_country] => US
[patent_app_date] => 2013-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14095704
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/095704 | Warpage reduction in structures with electrical circuitry | Dec 2, 2013 | Issued |
Array
(
[id] => 11508713
[patent_doc_number] => 09599866
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Active matrix substrate and display device'
[patent_app_type] => utility
[patent_app_number] => 14/438683
[patent_app_country] => US
[patent_app_date] => 2013-11-01
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438683
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438683 | Active matrix substrate and display device | Oct 31, 2013 | Issued |
Array
(
[id] => 11360249
[patent_doc_number] => 09536905
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-03
[patent_title] => 'Active matrix substrate and display device using same'
[patent_app_type] => utility
[patent_app_number] => 14/438697
[patent_app_country] => US
[patent_app_date] => 2013-11-01
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438697
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438697 | Active matrix substrate and display device using same | Oct 31, 2013 | Issued |
Array
(
[id] => 11220120
[patent_doc_number] => 09448454
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-20
[patent_title] => 'Active matrix substrate and display device'
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[patent_app_number] => 14/438678
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438678
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438678 | Active matrix substrate and display device | Oct 31, 2013 | Issued |
Array
(
[id] => 10426199
[patent_doc_number] => 20150311210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-29
[patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/439074
[patent_app_country] => US
[patent_app_date] => 2013-10-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/439074 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE | Oct 22, 2013 | Abandoned |
Array
(
[id] => 10394864
[patent_doc_number] => 20150279871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-01
[patent_title] => 'SEMICONDUCTOR DEVICE, DISPLAY UNIT, AND ELECTRONIC APPARATUS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438937 | SEMICONDUCTOR DEVICE, DISPLAY UNIT, AND ELECTRONIC APPARATUS | Oct 9, 2013 | Abandoned |
Array
(
[id] => 11453656
[patent_doc_number] => 09577310
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-21
[patent_title] => 'Semiconductor package and semiconductor package mounting structure'
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[patent_app_number] => 14/438734
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/438734 | Semiconductor package and semiconductor package mounting structure | Jun 24, 2013 | Issued |
Array
(
[id] => 10645471
[patent_doc_number] => 09362349
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'Semiconductor device with charge carrier lifetime reduction means'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/923436 | Semiconductor device with charge carrier lifetime reduction means | Jun 20, 2013 | Issued |
Array
(
[id] => 9106101
[patent_doc_number] => 20130279233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/921554
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921554 | VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME | Jun 18, 2013 | Abandoned |
Array
(
[id] => 10929790
[patent_doc_number] => 20140332811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-13
[patent_title] => 'SEMICONDUCTOR DEVICE WITH BOND AND PROBE PADS'
[patent_app_type] => utility
[patent_app_number] => 13/892297
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[patent_app_date] => 2013-05-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/892297 | SEMICONDUCTOR DEVICE WITH BOND AND PROBE PADS | May 11, 2013 | Abandoned |
Array
(
[id] => 10929821
[patent_doc_number] => 20140332842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-13
[patent_title] => 'PACKAGED OVERVOLTAGE PROTECTION CIRCUIT FOR TRIGGERING THYRISTORS'
[patent_app_type] => utility
[patent_app_number] => 13/892237
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/892237 | Packaged overvoltage protection circuit for triggering thyristors | May 9, 2013 | Issued |
Array
(
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[patent_title] => 'A PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/892191 | Process method and structure for high voltage MOSFETs | May 9, 2013 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/835463 | Extremely thin semiconductor-on-insulator (ETSOI) layer | Mar 14, 2013 | Issued |