Jeffrey E. Madonna

Array ( [id] => 12033590 [patent_doc_number] => 20170323689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'LEVERAGING CHIP VARIABILITY' [patent_app_type] => utility [patent_app_number] => 15/462730 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4868 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710246 [patent_doc_number] => 20170178745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY AND READ SENSING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/450503 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12207 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11615315 [patent_doc_number] => 09653177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'One time programmable non-volatile memory and read sensing method thereof' [patent_app_type] => utility [patent_app_number] => 15/408942 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12202220 [patent_doc_number] => 09905291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Circuit and method of generating a sense amplifier enable signal' [patent_app_type] => utility [patent_app_number] => 15/400475 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13084725 [patent_doc_number] => 10062433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Apparatuses and methods of reading memory cells [patent_app_type] => utility [patent_app_number] => 15/399530 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6717 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11572011 [patent_doc_number] => 20170110655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SPIN TORQUE MRAM BASED ON CO, IR SYNTHETIC ANTIFERROMAGNETIC MULTILAYER' [patent_app_type] => utility [patent_app_number] => 15/390121 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13908665 [patent_doc_number] => 20190043537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => LAYERED SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/070738 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11659893 [patent_doc_number] => 09672904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-06 [patent_title] => '6T bitcell for single port static random access memories (SRAM) with single-ended read and single-ended write' [patent_app_type] => utility [patent_app_number] => 15/373633 [patent_app_country] => US [patent_app_date] => 2016-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2447 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11883466 [patent_doc_number] => 09754646 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Voltage stress tolerant high speed memory driver having flying capacitor circuit' [patent_app_type] => utility [patent_app_number] => 15/342974 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8325 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12154505 [patent_doc_number] => 20180025769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'REFRESH CONTROL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/342436 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12208324 [patent_doc_number] => 20180053550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'LOW POWER ANALOG OR MULTI-LEVEL MEMORY FOR NEUROMORPHIC COMPUTING' [patent_app_type] => utility [patent_app_number] => 15/343182 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11861752 [patent_doc_number] => 09741440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Memory device and read method of memory device' [patent_app_type] => utility [patent_app_number] => 15/294849 [patent_app_country] => US [patent_app_date] => 2016-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 12799 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15294849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12088906 [patent_doc_number] => 09842639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Systems and methods for managing read voltages in a cross-point memory array' [patent_app_type] => utility [patent_app_number] => 15/288874 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13005605 [patent_doc_number] => 10026473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Non-volatile memory device for selectively performing recovery operation and method of operating the same [patent_app_type] => utility [patent_app_number] => 15/288758 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12214695 [patent_doc_number] => 09911510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-06 [patent_title] => 'Redundancy schemes for memory cell repair' [patent_app_type] => utility [patent_app_number] => 15/288832 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12631542 [patent_doc_number] => 20180102344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE [patent_app_type] => utility [patent_app_number] => 15/287344 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12334137 [patent_doc_number] => 09947379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Device and methods for writing and erasing analog information in small memory units via voltage pulses [patent_app_type] => utility [patent_app_number] => 15/287552 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3657 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11571516 [patent_doc_number] => 20170110159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR THE SAME' [patent_app_type] => utility [patent_app_number] => 15/283624 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10060 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11352464 [patent_doc_number] => 20160371204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVICE IMPLEMENTING A JEDEC STANDARD DDR-4 LRDIMM CHIPSET' [patent_app_type] => utility [patent_app_number] => 15/251147 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4201 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12553455 [patent_doc_number] => 10014040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor apparatus, semiconductor system, and system relating to dual clock transmission [patent_app_type] => utility [patent_app_number] => 15/246893 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246893 [rel_patent_id] =>[rel_patent_doc_number] =>)