Search

Jeffrey E Russel

Examiner (ID: 7840, Phone: (571)272-0969 , Office: P/1675 )

Most Active Art Unit
1654
Art Unit(s)
1103, 1815, 1653, 1654, 1809, 1811, 2899, 1675, 1621
Total Applications
3490
Issued Applications
2338
Pending Applications
315
Abandoned Applications
837

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1197177 [patent_doc_number] => 06732323 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method of selecting initialization parameters for multi-channel data communication with forward error correction' [patent_app_type] => B1 [patent_app_number] => 09/689367 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 11256 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732323.pdf [firstpage_image] =>[orig_patent_app_number] => 09689367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689367
Method of selecting initialization parameters for multi-channel data communication with forward error correction Oct 11, 2000 Issued
Array ( [id] => 1234565 [patent_doc_number] => 06697980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Die fault testing utilizing an exclusive-or network of gates' [patent_app_type] => B1 [patent_app_number] => 09/686469 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 3 [patent_no_of_words] => 2580 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697980.pdf [firstpage_image] =>[orig_patent_app_number] => 09686469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686469
Die fault testing utilizing an exclusive-or network of gates Oct 9, 2000 Issued
Array ( [id] => 1225949 [patent_doc_number] => 06704897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Semiconductor device and the test system for the same' [patent_app_type] => B1 [patent_app_number] => 09/669577 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4772 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704897.pdf [firstpage_image] =>[orig_patent_app_number] => 09669577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669577
Semiconductor device and the test system for the same Sep 25, 2000 Issued
Array ( [id] => 1197147 [patent_doc_number] => 06732308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Integration of embedded and test mode timer' [patent_app_type] => B1 [patent_app_number] => 09/664819 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732308.pdf [firstpage_image] =>[orig_patent_app_number] => 09664819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664819
Integration of embedded and test mode timer Sep 18, 2000 Issued
Array ( [id] => 7622304 [patent_doc_number] => 06687862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Apparatus and method for fast memory fault analysis' [patent_app_type] => B1 [patent_app_number] => 09/663307 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3800 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687862.pdf [firstpage_image] =>[orig_patent_app_number] => 09663307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663307
Apparatus and method for fast memory fault analysis Sep 14, 2000 Issued
Array ( [id] => 1234590 [patent_doc_number] => 06697989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method and apparatus for error correction' [patent_app_type] => B1 [patent_app_number] => 09/657779 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10837 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697989.pdf [firstpage_image] =>[orig_patent_app_number] => 09657779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657779
Method and apparatus for error correction Sep 7, 2000 Issued
Array ( [id] => 1062298 [patent_doc_number] => 06854079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Apparatus and method for reducing test resources in testing Rambus DRAMs' [patent_app_type] => utility [patent_app_number] => 09/653112 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4634 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854079.pdf [firstpage_image] =>[orig_patent_app_number] => 09653112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653112
Apparatus and method for reducing test resources in testing Rambus DRAMs Aug 30, 2000 Issued
Array ( [id] => 7962139 [patent_doc_number] => 06681360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Fault detection method for electronic circuit' [patent_app_type] => B1 [patent_app_number] => 09/552765 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3938 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681360.pdf [firstpage_image] =>[orig_patent_app_number] => 09552765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552765
Fault detection method for electronic circuit Apr 18, 2000 Issued
Array ( [id] => 7622298 [patent_doc_number] => 06687868 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Test device and method for electrically testing electronic device' [patent_app_type] => B1 [patent_app_number] => 09/543416 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6693 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687868.pdf [firstpage_image] =>[orig_patent_app_number] => 09543416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543416
Test device and method for electrically testing electronic device Apr 4, 2000 Issued
Array ( [id] => 1181500 [patent_doc_number] => 06754863 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Scan interface chip (SIC) system and method for scan testing electronic systems' [patent_app_type] => B1 [patent_app_number] => 09/542431 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 29612 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754863.pdf [firstpage_image] =>[orig_patent_app_number] => 09542431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542431
Scan interface chip (SIC) system and method for scan testing electronic systems Apr 3, 2000 Issued
Array ( [id] => 1177994 [patent_doc_number] => 06760876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Scan interface chip (SIC) system and method for scan testing electronic systems' [patent_app_type] => B1 [patent_app_number] => 09/542791 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 29659 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760876.pdf [firstpage_image] =>[orig_patent_app_number] => 09542791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542791
Scan interface chip (SIC) system and method for scan testing electronic systems Apr 3, 2000 Issued
Array ( [id] => 1109988 [patent_doc_number] => 06813739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Scan interface chip (SIC) system and method for scan testing electronic systems' [patent_app_type] => B1 [patent_app_number] => 09/543023 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 29592 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813739.pdf [firstpage_image] =>[orig_patent_app_number] => 09543023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543023
Scan interface chip (SIC) system and method for scan testing electronic systems Apr 3, 2000 Issued
Array ( [id] => 7628137 [patent_doc_number] => 06820224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method and system for increasing yield in embedded memory devices' [patent_app_type] => B1 [patent_app_number] => 09/542174 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1501 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820224.pdf [firstpage_image] =>[orig_patent_app_number] => 09542174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542174
Method and system for increasing yield in embedded memory devices Apr 3, 2000 Issued
Array ( [id] => 1250305 [patent_doc_number] => 06675329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Internal memory in application specific integrated circuit device and method for testing internal memory' [patent_app_type] => B1 [patent_app_number] => 09/541698 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3578 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675329.pdf [firstpage_image] =>[orig_patent_app_number] => 09541698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541698
Internal memory in application specific integrated circuit device and method for testing internal memory Apr 2, 2000 Issued
Array ( [id] => 1207004 [patent_doc_number] => 06721908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Interleaving/deinterleaving apparatus and method for a communication system' [patent_app_type] => B1 [patent_app_number] => 09/541816 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721908.pdf [firstpage_image] =>[orig_patent_app_number] => 09541816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541816
Interleaving/deinterleaving apparatus and method for a communication system Apr 2, 2000 Issued
Array ( [id] => 1362205 [patent_doc_number] => 06587983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Apparatus and method of testing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/541911 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7608 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587983.pdf [firstpage_image] =>[orig_patent_app_number] => 09541911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541911
Apparatus and method of testing a semiconductor device Apr 2, 2000 Issued
Array ( [id] => 1225990 [patent_doc_number] => 06704904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method and apparatus for permuting code sequences and initial context of code sequences for improved electrical verification' [patent_app_type] => B1 [patent_app_number] => 09/541253 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4771 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704904.pdf [firstpage_image] =>[orig_patent_app_number] => 09541253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541253
Method and apparatus for permuting code sequences and initial context of code sequences for improved electrical verification Apr 2, 2000 Issued
Array ( [id] => 1421855 [patent_doc_number] => 06543028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Silent data corruption prevention due to instruction corruption by soft errors' [patent_app_type] => B1 [patent_app_number] => 09/540295 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3014 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/543/06543028.pdf [firstpage_image] =>[orig_patent_app_number] => 09540295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540295
Silent data corruption prevention due to instruction corruption by soft errors Mar 30, 2000 Issued
Array ( [id] => 1382522 [patent_doc_number] => 06574762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Use of a scan chain for configuration of BIST unit operation' [patent_app_type] => B1 [patent_app_number] => 09/540197 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5611 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574762.pdf [firstpage_image] =>[orig_patent_app_number] => 09540197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540197
Use of a scan chain for configuration of BIST unit operation Mar 30, 2000 Issued
Array ( [id] => 1311778 [patent_doc_number] => 06625765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Memory based phase locked loop' [patent_app_type] => B1 [patent_app_number] => 09/538989 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625765.pdf [firstpage_image] =>[orig_patent_app_number] => 09538989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538989
Memory based phase locked loop Mar 29, 2000 Issued
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