Search

Jeffrey E Russel

Examiner (ID: 7840, Phone: (571)272-0969 , Office: P/1675 )

Most Active Art Unit
1654
Art Unit(s)
1103, 1815, 1653, 1654, 1809, 1811, 2899, 1675, 1621
Total Applications
3490
Issued Applications
2338
Pending Applications
315
Abandoned Applications
837

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7962149 [patent_doc_number] => 06681355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Analog boundary scan compliant integrated circuit system' [patent_app_type] => B1 [patent_app_number] => 09/538260 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6265 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681355.pdf [firstpage_image] =>[orig_patent_app_number] => 09538260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538260
Analog boundary scan compliant integrated circuit system Mar 29, 2000 Issued
Array ( [id] => 1396592 [patent_doc_number] => 06567953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and apparatus for host-based validating of data transferred between a device and a host' [patent_app_type] => B1 [patent_app_number] => 09/538600 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6579 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567953.pdf [firstpage_image] =>[orig_patent_app_number] => 09538600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538600
Method and apparatus for host-based validating of data transferred between a device and a host Mar 28, 2000 Issued
Array ( [id] => 7629940 [patent_doc_number] => 06636999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Clock adjusting method and circuit device' [patent_app_type] => B1 [patent_app_number] => 09/537776 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6411 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636999.pdf [firstpage_image] =>[orig_patent_app_number] => 09537776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537776
Clock adjusting method and circuit device Mar 28, 2000 Issued
Array ( [id] => 1311800 [patent_doc_number] => 06625768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Test bus architecture' [patent_app_type] => B1 [patent_app_number] => 09/537398 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4304 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625768.pdf [firstpage_image] =>[orig_patent_app_number] => 09537398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537398
Test bus architecture Mar 28, 2000 Issued
Array ( [id] => 7629934 [patent_doc_number] => 06637005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Triple redundant self-scrubbing integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/516260 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1823 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/637/06637005.pdf [firstpage_image] =>[orig_patent_app_number] => 09516260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516260
Triple redundant self-scrubbing integrated circuit Feb 28, 2000 Issued
Array ( [id] => 1348677 [patent_doc_number] => 06598192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and apparatus for testing an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/513867 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3838 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598192.pdf [firstpage_image] =>[orig_patent_app_number] => 09513867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513867
Method and apparatus for testing an integrated circuit Feb 27, 2000 Issued
09/486468 DEFINING QUALITY OF TRANSMISSION IN A TRANSMISSION SYSTEM Feb 27, 2000 Abandoned
Array ( [id] => 1311849 [patent_doc_number] => 06625775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Encoder/decoder with serial concatenated structure in communication system' [patent_app_type] => B1 [patent_app_number] => 09/459050 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4305 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625775.pdf [firstpage_image] =>[orig_patent_app_number] => 09459050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459050
Encoder/decoder with serial concatenated structure in communication system Dec 9, 1999 Issued
Array ( [id] => 1412753 [patent_doc_number] => 06553537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Reed-Solomon decoding apparatus and control method therefor' [patent_app_type] => B1 [patent_app_number] => 09/457727 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9715 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553537.pdf [firstpage_image] =>[orig_patent_app_number] => 09457727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457727
Reed-Solomon decoding apparatus and control method therefor Dec 9, 1999 Issued
Array ( [id] => 1337682 [patent_doc_number] => 06604224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method of performing content integrity analysis of a data stream' [patent_app_type] => B1 [patent_app_number] => 09/459217 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4701 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604224.pdf [firstpage_image] =>[orig_patent_app_number] => 09459217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459217
Method of performing content integrity analysis of a data stream Dec 9, 1999 Issued
Array ( [id] => 1386668 [patent_doc_number] => 06571364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Semiconductor integrated circuit device with fault analysis function' [patent_app_type] => B1 [patent_app_number] => 09/457530 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 39 [patent_no_of_words] => 15950 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571364.pdf [firstpage_image] =>[orig_patent_app_number] => 09457530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457530
Semiconductor integrated circuit device with fault analysis function Dec 8, 1999 Issued
Array ( [id] => 1431972 [patent_doc_number] => 06516431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/457396 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 47 [patent_no_of_words] => 11327 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516431.pdf [firstpage_image] =>[orig_patent_app_number] => 09457396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457396
Semiconductor device Dec 8, 1999 Issued
Array ( [id] => 1407814 [patent_doc_number] => 06560742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Parallel system and method for cyclic redundancy checking (CRC) generation' [patent_app_type] => B1 [patent_app_number] => 09/457950 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5374 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560742.pdf [firstpage_image] =>[orig_patent_app_number] => 09457950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457950
Parallel system and method for cyclic redundancy checking (CRC) generation Dec 8, 1999 Issued
Array ( [id] => 1325774 [patent_doc_number] => 06615379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method and apparatus for testing a logic device' [patent_app_type] => B1 [patent_app_number] => 09/457255 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1438 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615379.pdf [firstpage_image] =>[orig_patent_app_number] => 09457255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457255
Method and apparatus for testing a logic device Dec 7, 1999 Issued
Array ( [id] => 6689845 [patent_doc_number] => 20030033571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'ENCODING APPARATUS AND ENCODING METHOD FOR MULTIDIMENSIONALLY CODING AND ENCODING METHOD AND DECODING APPARATUS FOR ITERATIVE DECODING OF MULTIDIMENSIONALLY CODED INFORMATION' [patent_app_type] => new [patent_app_number] => 09/456376 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4010 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033571.pdf [firstpage_image] =>[orig_patent_app_number] => 09456376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456376
Encoding apparatus and encoding method for multidimensionally coding and encoding method and decoding apparatus for iterative decoding of multidimensionally coded information Dec 7, 1999 Issued
Array ( [id] => 1402043 [patent_doc_number] => 06564346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Advanced bit fail map compression with fail signature analysis' [patent_app_type] => B1 [patent_app_number] => 09/455855 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7301 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564346.pdf [firstpage_image] =>[orig_patent_app_number] => 09455855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455855
Advanced bit fail map compression with fail signature analysis Dec 6, 1999 Issued
Array ( [id] => 1339893 [patent_doc_number] => 06601197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/456259 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7996 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601197.pdf [firstpage_image] =>[orig_patent_app_number] => 09456259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456259
Semiconductor memory device Dec 6, 1999 Issued
Array ( [id] => 1362118 [patent_doc_number] => 06587977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'o,k,m,/m recording code' [patent_app_type] => B1 [patent_app_number] => 09/455624 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8464 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587977.pdf [firstpage_image] =>[orig_patent_app_number] => 09455624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455624
o,k,m,/m recording code Dec 5, 1999 Issued
Array ( [id] => 1573864 [patent_doc_number] => 06499119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Data inspection method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/455372 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499119.pdf [firstpage_image] =>[orig_patent_app_number] => 09455372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455372
Data inspection method and apparatus Dec 5, 1999 Issued
Array ( [id] => 1429619 [patent_doc_number] => 06530045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Apparatus and method for testing rambus DRAMs' [patent_app_type] => B1 [patent_app_number] => 09/454808 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4154 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530045.pdf [firstpage_image] =>[orig_patent_app_number] => 09454808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454808
Apparatus and method for testing rambus DRAMs Dec 2, 1999 Issued
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