Jeffrey L Sterrett

Array ( [id] => 8650561 [patent_doc_number] => 20130036291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS' [patent_app_type] => utility [patent_app_number] => 13/650227 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5021 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9680443 [patent_doc_number] => 08819370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-26 [patent_title] => 'Techniques for storage lifecycle policy management' [patent_app_type] => utility [patent_app_number] => 13/631603 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7747 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8588554 [patent_doc_number] => 20130007374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Checkpointed Tag Prefetcher' [patent_app_type] => utility [patent_app_number] => 13/610071 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8504449 [patent_doc_number] => 20120303857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Checkpointed Tag Prefetcher' [patent_app_type] => utility [patent_app_number] => 13/564829 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4143 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9102633 [patent_doc_number] => 08566526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Combined transparent/non-transparent cache' [patent_app_type] => utility [patent_app_number] => 13/545526 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9207570 [patent_doc_number] => 20140006747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SYSTEMS AND METHODS FOR PROCESSING INSTRUCTIONS WHEN UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/538251 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8221 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10536697 [patent_doc_number] => 09262327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Signature based hit-predicting cache' [patent_app_type] => utility [patent_app_number] => 13/538390 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 16632 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8395570 [patent_doc_number] => 20120233412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/477513 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2939 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8861452 [patent_doc_number] => 08464005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Accessing common registers in a multi-core processor' [patent_app_type] => utility [patent_app_number] => 13/464689 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9430914 [patent_doc_number] => 08706999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Method and system for cascaded flashcopy zoning and algorithm and/or computer program code and method implementing the same' [patent_app_type] => utility [patent_app_number] => 13/453367 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3492 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8678566 [patent_doc_number] => 08386701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Apparatus and method for multi-level cache utilization' [patent_app_type] => utility [patent_app_number] => 13/450882 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8703802 [patent_doc_number] => 08397037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Automatic association of reference data with primary process data based on time and shared identifier' [patent_app_type] => utility [patent_app_number] => 13/437866 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8632827 [patent_doc_number] => 08364926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Memory module with reduced access granularity' [patent_app_type] => utility [patent_app_number] => 13/408950 [patent_app_country] => US [patent_app_date] => 2012-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 9786 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13408950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9665810 [patent_doc_number] => 08812818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Management of persistent memory in a multi-node computer system' [patent_app_type] => utility [patent_app_number] => 13/372609 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4545 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8045889 [patent_doc_number] => 20120072682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-22 [patent_title] => 'DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION' [patent_app_type] => utility [patent_app_number] => 13/308333 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6259 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20120072682.pdf [firstpage_image] =>[orig_patent_app_number] => 13308333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8831592 [patent_doc_number] => 20130132637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'Kernel Memory Locking For Systems that Allow Over-Commitment Memory' [patent_app_type] => utility [patent_app_number] => 13/299463 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5596 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8831623 [patent_doc_number] => 20130132668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'VOLUME COPY MANAGEMENT METHOD ON THIN PROVISIONING POOL OF STORAGE SUBSYSTEM' [patent_app_type] => utility [patent_app_number] => 13/299705 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8831653 [patent_doc_number] => 20130132698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'HIGH-EFFICIENCY VIRTUAL DISK MANAGEMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/299353 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4393 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9885906 [patent_doc_number] => 08972691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Addressing cross-allocated blocks in a file system' [patent_app_type] => utility [patent_app_number] => 13/288376 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11345323 [patent_doc_number] => 09529729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Location of memory management translations in an emulated processor' [patent_app_type] => utility [patent_app_number] => 13/288506 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3263 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288506 [rel_patent_id] =>[rel_patent_doc_number] =>)