Search

Jeffrey S. Lenihan

Examiner (ID: 6521, Phone: (571)270-5452 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
980
Issued Applications
658
Pending Applications
84
Abandoned Applications
255

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18219532 [patent_doc_number] => 11594481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Package, method for forming a package, carrier tape, chip card and method for forming a carrier tape [patent_app_type] => utility [patent_app_number] => 17/333313 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 11146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333313
Package, method for forming a package, carrier tape, chip card and method for forming a carrier tape May 27, 2021 Issued
Array ( [id] => 18040126 [patent_doc_number] => 20220384343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => POWER GATING SWITCH TREE STRUCTURE FOR REDUCED WAKE-UP TIME AND POWER LEAKAGE [patent_app_type] => utility [patent_app_number] => 17/331450 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331450
Power gating switch tree structure for reduced wake-up time and power leakage May 25, 2021 Issued
Array ( [id] => 18682479 [patent_doc_number] => 20230320159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DOUBLE-SIDED DISPLAY PANEL AND DOUBLE-SIDED DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/311796 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311796
DOUBLE-SIDED DISPLAY PANEL AND DOUBLE-SIDED DISPLAY DEVICE May 17, 2021 Abandoned
Array ( [id] => 17055996 [patent_doc_number] => 20210265430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => OLED ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/318528 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318528
OLED array substrate, display panel and display device May 11, 2021 Issued
Array ( [id] => 17056094 [patent_doc_number] => 20210265528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => SILICON-BASED SUBSTRATE, SUBSTRATE, MANUFACTURING METHOD THEREOF, AND OPTOELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/245995 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245995
SILICON-BASED SUBSTRATE, SUBSTRATE, MANUFACTURING METHOD THEREOF, AND OPTOELECTRONIC DEVICE Apr 29, 2021 Abandoned
Array ( [id] => 17025181 [patent_doc_number] => 20210249053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => LANDING PAD IN INTERCONNECT AND MEMORY STACKS: STRUCTURE AND FORMATION OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/241796 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241796
LANDING PAD IN INTERCONNECT AND MEMORY STACKS: STRUCTURE AND FORMATION OF THE SAME Apr 26, 2021 Abandoned
Array ( [id] => 17963659 [patent_doc_number] => 20220344240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MULTILAYER SUPERCONDUCTING STRUCTURES FOR CRYOGENIC ELECTRONICS [patent_app_type] => utility [patent_app_number] => 17/239458 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239458
MULTILAYER SUPERCONDUCTING STRUCTURES FOR CRYOGENIC ELECTRONICS Apr 22, 2021 Pending
Array ( [id] => 18360177 [patent_doc_number] => 20230141768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => DISPLAY PANEL HAVING BLIND HOLE TO ACCOMODATE SIGNALS EXCHANGED WITH UNDER-DISPLAY COMPONENT [patent_app_type] => utility [patent_app_number] => 17/917900 [patent_app_country] => US [patent_app_date] => 2021-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17917900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/917900
DISPLAY PANEL HAVING BLIND HOLE TO ACCOMODATE SIGNALS EXCHANGED WITH UNDER-DISPLAY COMPONENT Apr 8, 2021 Pending
Array ( [id] => 16981769 [patent_doc_number] => 20210226006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/225452 [patent_app_country] => US [patent_app_date] => 2021-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17225452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/225452
Silicon and silicon germanium nanowire structures Apr 7, 2021 Issued
Array ( [id] => 17709742 [patent_doc_number] => 20220209750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => QUALITY FACTOR OF A PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 17/223792 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223792
QUALITY FACTOR OF A PARASITIC CAPACITANCE Apr 5, 2021 Pending
Array ( [id] => 19376579 [patent_doc_number] => 12068159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Methods and apparatus for mask patterning debris removal [patent_app_type] => utility [patent_app_number] => 17/219082 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219082
Methods and apparatus for mask patterning debris removal Mar 30, 2021 Issued
Array ( [id] => 19494334 [patent_doc_number] => 12113058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Display device with a static electricity discharging circuit [patent_app_type] => utility [patent_app_number] => 17/215682 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7075 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215682
Display device with a static electricity discharging circuit Mar 28, 2021 Issued
Array ( [id] => 17870776 [patent_doc_number] => 20220293513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => POWER DECOUPLING METAL-INSULATOR-METAL CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/198941 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198941
POWER DECOUPLING METAL-INSULATOR-METAL CAPACITOR Mar 10, 2021 Abandoned
Array ( [id] => 17070657 [patent_doc_number] => 20210272874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => POWER MODULE HOUSING WITH IMPROVED PROTRUSION DESIGN [patent_app_type] => utility [patent_app_number] => 17/182741 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182741
POWER MODULE HOUSING WITH IMPROVED PROTRUSION DESIGN Feb 22, 2021 Abandoned
Array ( [id] => 19138099 [patent_doc_number] => 11973075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Dual substrate side ESD diode for high speed circuit [patent_app_type] => utility [patent_app_number] => 17/181196 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181196
Dual substrate side ESD diode for high speed circuit Feb 21, 2021 Issued
Array ( [id] => 16888975 [patent_doc_number] => 20210175172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/180094 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180094
Semiconductor integrated circuit device Feb 18, 2021 Issued
Array ( [id] => 16873847 [patent_doc_number] => 20210167314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/169906 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169906
Display device including carrier generation layers Feb 7, 2021 Issued
Array ( [id] => 17347193 [patent_doc_number] => 20220013524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/158790 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158790
Three-dimensional semiconductor device with air gap Jan 25, 2021 Issued
Array ( [id] => 16937000 [patent_doc_number] => 20210202889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => DISPLAY PANEL AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/138179 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138179
Display panel having cathode electrode in contact with connection electrode in shade region and method of manufacturing same Dec 29, 2020 Issued
Array ( [id] => 17708820 [patent_doc_number] => 20220208828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHODS FOR INTEGRATION OF LIGHT EMITTING DIODES AND IMAGE SENSORS [patent_app_type] => utility [patent_app_number] => 17/137606 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137606
Methods for integration of light emitting diodes and image sensors Dec 29, 2020 Issued
Menu