Jeffrey T. Knapp

Array ( [id] => 8948200 [patent_doc_number] => 20130193980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs' [patent_app_type] => utility [patent_app_number] => 13/359921 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3665 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13359921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9611802 [patent_doc_number] => 08788991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'State grouping for element utilization' [patent_app_type] => utility [patent_app_number] => 13/357511 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12403 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8959181 [patent_doc_number] => 08504975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Reliability evaluation and system fail warning methods using on chip parametric monitors' [patent_app_type] => utility [patent_app_number] => 13/344178 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3031 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13344178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8787178 [patent_doc_number] => 08434034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method of making optical proximity correction to original gate photomask pattern based on different substrate areas' [patent_app_type] => utility [patent_app_number] => 13/339411 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1968 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9458733 [patent_doc_number] => 08719760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Validating integrated circuit simulation results' [patent_app_type] => utility [patent_app_number] => 13/340329 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13340329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9768590 [patent_doc_number] => 20140292253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'VEHICLE COMPRISING BATTERY' [patent_app_type] => utility [patent_app_number] => 13/580246 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3534 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9195698 [patent_doc_number] => 20130335013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'ELECTRIC POWER TOOL POWERED BY A PLURALITY OF RECHARGEABLE BATTERY CELLS' [patent_app_type] => utility [patent_app_number] => 13/985345 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5175 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9169969 [patent_doc_number] => 08595664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Guiding design actions for complex failure modes' [patent_app_type] => utility [patent_app_number] => 13/328911 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9491 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13328911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8769539 [patent_doc_number] => 20130097576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR CHECKING VIA STUB' [patent_app_type] => utility [patent_app_number] => 13/327771 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13327771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8881424 [patent_doc_number] => 20130154608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'DETERMINING ALIGNMENT USING A SPATIALLY VARYING CHARGE DISTRIBUTION' [patent_app_type] => utility [patent_app_number] => 13/326301 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8873101 [patent_doc_number] => 08468490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Electronic device and method for checking layout of printed circuit board' [patent_app_type] => utility [patent_app_number] => 13/315291 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1987 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8843494 [patent_doc_number] => 20130139122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'Method of, and Apparatus for, Data Path Optimisation in Parallel Pipelined Hardware' [patent_app_type] => utility [patent_app_number] => 13/305261 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11635 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13305261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7819659 [patent_doc_number] => 20120066279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Techniques for Use with Automated Circuit Design and Simulations' [patent_app_type] => utility [patent_app_number] => 13/301745 [patent_app_country] => US [patent_app_date] => 2011-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5635 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066279.pdf [firstpage_image] =>[orig_patent_app_number] => 13301745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8716250 [patent_doc_number] => 08402404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Stacked die interconnect validation' [patent_app_type] => utility [patent_app_number] => 13/298541 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9023656 [patent_doc_number] => 08533655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-10 [patent_title] => 'Method and apparatus for capturing data samples with test circuitry' [patent_app_type] => utility [patent_app_number] => 13/296511 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8837309 [patent_doc_number] => 08453078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Integrated circuit transformer devices for on-chip millimeter-wave applications' [patent_app_type] => utility [patent_app_number] => 13/292585 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6765 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8230142 [patent_doc_number] => 20120144350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'GATE MODELING FOR SEMICONDUCTOR FABRICATION PROCESS EFFECTS' [patent_app_type] => utility [patent_app_number] => 13/286004 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5052 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8716264 [patent_doc_number] => 08402416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method and apparatus for composing and decomposing low-skew networks' [patent_app_type] => utility [patent_app_number] => 13/267334 [patent_app_country] => US [patent_app_date] => 2011-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5446 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13267334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7760144 [patent_doc_number] => 20120030638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 13/253651 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5094 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030638.pdf [firstpage_image] =>[orig_patent_app_number] => 13253651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11788022 [patent_doc_number] => 09397506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Voltage management device for a stacked battery' [patent_app_type] => utility [patent_app_number] => 14/006224 [patent_app_country] => US [patent_app_date] => 2011-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14006224 [rel_patent_id] =>[rel_patent_doc_number] =>)