
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8189456
[patent_doc_number] => 20120117523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-10
[patent_title] => 'INVERSE LITHOGRAPHY FOR HIGH TRANSMISSION ATTENUATED PHASE SHIFT MASK DESIGN AND CREATION'
[patent_app_type] => utility
[patent_app_number] => 13/250971
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20120117523.pdf
[firstpage_image] =>[orig_patent_app_number] => 13250971
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250971 | Inverse lithography for high transmission attenuated phase shift mask design and creation | Sep 29, 2011 | Issued |
Array
(
[id] => 9257964
[patent_doc_number] => 08621407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-31
[patent_title] => 'Apparatus and method for supporting circuit design, and semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 13/236231
[patent_app_country] => US
[patent_app_date] => 2011-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 7100
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236231
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/236231 | Apparatus and method for supporting circuit design, and semiconductor integrated circuit | Sep 18, 2011 | Issued |
Array
(
[id] => 7813519
[patent_doc_number] => 08136057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-13
[patent_title] => 'Semiconductor device manufacturing method, data generating apparatus, data generating method and recording medium readable by computer recorded with data generating program'
[patent_app_type] => utility
[patent_app_number] => 13/223782
[patent_app_country] => US
[patent_app_date] => 2011-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 32
[patent_no_of_words] => 11069
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/136/08136057.pdf
[firstpage_image] =>[orig_patent_app_number] => 13223782
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/223782 | Semiconductor device manufacturing method, data generating apparatus, data generating method and recording medium readable by computer recorded with data generating program | Aug 31, 2011 | Issued |
Array
(
[id] => 8971859
[patent_doc_number] => 08510689
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-13
[patent_title] => 'Method and system for implementing context simulation'
[patent_app_type] => utility
[patent_app_number] => 13/210179
[patent_app_country] => US
[patent_app_date] => 2011-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 7429
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210179
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/210179 | Method and system for implementing context simulation | Aug 14, 2011 | Issued |
Array
(
[id] => 9509194
[patent_doc_number] => 20140145685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-29
[patent_title] => 'Battery System and Method for Determining Battery Module Voltages'
[patent_app_type] => utility
[patent_app_number] => 13/825284
[patent_app_country] => US
[patent_app_date] => 2011-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2636
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825284
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/825284 | Battery system and method for determining battery module voltages | Aug 11, 2011 | Issued |
Array
(
[id] => 9001899
[patent_doc_number] => 20130223024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-29
[patent_title] => 'CONTROL UNIT AND METHOD FOR DESIGNING A CIRCUIT BOARD OF A CONTROL UNIT'
[patent_app_type] => utility
[patent_app_number] => 13/820561
[patent_app_country] => US
[patent_app_date] => 2011-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3663
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13820561
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/820561 | Control unit and method for designing a circuit board of a control unit | Jul 11, 2011 | Issued |
Array
(
[id] => 10643997
[patent_doc_number] => 09360863
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'Data perturbation for wafer inspection or metrology setup using a model of a difference'
[patent_app_type] => utility
[patent_app_number] => 13/258441
[patent_app_country] => US
[patent_app_date] => 2011-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 7451
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13258441
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/258441 | Data perturbation for wafer inspection or metrology setup using a model of a difference | Jun 8, 2011 | Issued |
Array
(
[id] => 8826376
[patent_doc_number] => 20130127421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'ARRANGEMENT AND METHOD FOR SAFELY DISCHARING AN ENERGY ACCUMULATOR'
[patent_app_type] => utility
[patent_app_number] => 13/698542
[patent_app_country] => US
[patent_app_date] => 2011-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13698542
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/698542 | Arrangement and method for safely discharging an energy accumulator | May 4, 2011 | Issued |
Array
(
[id] => 9116343
[patent_doc_number] => 08572535
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-29
[patent_title] => 'Thermal analysis based circuit design'
[patent_app_type] => utility
[patent_app_number] => 13/099329
[patent_app_country] => US
[patent_app_date] => 2011-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10937
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13099329
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/099329 | Thermal analysis based circuit design | May 1, 2011 | Issued |
Array
(
[id] => 8361013
[patent_doc_number] => 20120216170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-23
[patent_title] => 'PRINTED CIRCUIT BOARD LAYOUT DEVICE CAPABLE OF AUTOMATICALLY ARRANGING ENCAPSULATED COMPONENT AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/095861
[patent_app_country] => US
[patent_app_date] => 2011-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1716
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13095861
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/095861 | Printed circuit board layout device capable of automatically arranging encapsulated component and method thereof | Apr 27, 2011 | Issued |
Array
(
[id] => 8491591
[patent_doc_number] => 20120290998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/320291
[patent_app_country] => US
[patent_app_date] => 2011-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4486
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13320291
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/320291 | DEVICE PERFORMANCE PREDICTION METHOD AND DEVICE STRUCTURE OPTIMIZATION METHOD | Apr 25, 2011 | Abandoned |
Array
(
[id] => 8558301
[patent_doc_number] => 08332788
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-12-11
[patent_title] => 'Generating a module interface for partial reconfiguration design flows'
[patent_app_type] => utility
[patent_app_number] => 13/077544
[patent_app_country] => US
[patent_app_date] => 2011-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6689
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077544
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/077544 | Generating a module interface for partial reconfiguration design flows | Mar 30, 2011 | Issued |
Array
(
[id] => 6186090
[patent_doc_number] => 20110170197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-07-14
[patent_title] => 'Method of Fabricating a Photomask Used to Form a Lens'
[patent_app_type] => utility
[patent_app_number] => 13/076511
[patent_app_country] => US
[patent_app_date] => 2011-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 4718
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20110170197.pdf
[firstpage_image] =>[orig_patent_app_number] => 13076511
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/076511 | Method of fabricating a photomask used to form a lens | Mar 30, 2011 | Issued |
Array
(
[id] => 9260238
[patent_doc_number] => 20130342167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-26
[patent_title] => 'HYBRID ELECTRIC VEHICLE POWER MANAGEMENT SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 13/985340
[patent_app_country] => US
[patent_app_date] => 2011-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3184
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985340
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/985340 | Hybrid electric vehicle power management system | Mar 14, 2011 | Issued |
Array
(
[id] => 8849441
[patent_doc_number] => 08458641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-04
[patent_title] => 'Method, system, and design structure for making voltage environment consistent for reused sub modules in chip design'
[patent_app_type] => utility
[patent_app_number] => 13/031754
[patent_app_country] => US
[patent_app_date] => 2011-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 7886
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13031754
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/031754 | Method, system, and design structure for making voltage environment consistent for reused sub modules in chip design | Feb 21, 2011 | Issued |
Array
(
[id] => 8349357
[patent_doc_number] => 20120210283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-16
[patent_title] => 'ANALYSIS OF COMPENSATED LAYOUT SHAPES'
[patent_app_type] => utility
[patent_app_number] => 13/026451
[patent_app_country] => US
[patent_app_date] => 2011-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 10756
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026451
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/026451 | Analysis of compensated layout shapes | Feb 13, 2011 | Issued |
Array
(
[id] => 7820031
[patent_doc_number] => 20120066651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'Technique for Repairing a Reflective Photo-Mask'
[patent_app_type] => utility
[patent_app_number] => 13/024233
[patent_app_country] => US
[patent_app_date] => 2011-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10172
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20120066651.pdf
[firstpage_image] =>[orig_patent_app_number] => 13024233
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/024233 | Technique for repairing a reflective photo-mask | Feb 8, 2011 | Issued |
Array
(
[id] => 9077622
[patent_doc_number] => 08555214
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-08
[patent_title] => 'Technique for analyzing a reflective photo-mask'
[patent_app_type] => utility
[patent_app_number] => 13/021591
[patent_app_country] => US
[patent_app_date] => 2011-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6430
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13021591
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/021591 | Technique for analyzing a reflective photo-mask | Feb 3, 2011 | Issued |
Array
(
[id] => 8564105
[patent_doc_number] => 20120326675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'SYSTEM FOR PREVENTING DETERIORATION OF STORAGE CAPACITY OF LEAD ACID BATTERY AND REUSING LEAD ACID BATTERY BY ELECTRICAL TREATMENT'
[patent_app_type] => utility
[patent_app_number] => 13/578085
[patent_app_country] => US
[patent_app_date] => 2011-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1863
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578085
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/578085 | System for preventing deterioration of storage capacity of lead acid battery and reusing lead acid battery by electrical treatment | Feb 3, 2011 | Issued |
Array
(
[id] => 8810436
[patent_doc_number] => 08448103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Manufacturing features of different depth by placement of vias'
[patent_app_type] => utility
[patent_app_number] => 13/018551
[patent_app_country] => US
[patent_app_date] => 2011-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2940
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018551
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/018551 | Manufacturing features of different depth by placement of vias | Jan 31, 2011 | Issued |