Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8315109 [patent_doc_number] => 20120192134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'User Guided Short Correction And Schematic Fix Visualization' [patent_app_type] => utility [patent_app_number] => 13/012791 [patent_app_country] => US [patent_app_date] => 2011-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10699 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13012791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/012791
User Guided Short Correction And Schematic Fix Visualization Jan 23, 2011 Abandoned
Array ( [id] => 6170095 [patent_doc_number] => 20110175247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT PATTERN VERIFICATION METHOD, PHOTOMASK MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE MANUFACTURING METHOD, AND PROGRAM FOR IMPLEMENTING SEMICONDUCTOR INTEGRATED CIRCUIT PATTERN VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/010130 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4885 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20110175247.pdf [firstpage_image] =>[orig_patent_app_number] => 13010130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010130
Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method Jan 19, 2011 Issued
Array ( [id] => 8315115 [patent_doc_number] => 20120192135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'METHODS FOR ANALYZING CELLS OF A CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/010391 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13010391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010391
Methods for analyzing cells of a cell library Jan 19, 2011 Issued
Array ( [id] => 8716266 [patent_doc_number] => 08402419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'DSP design system level power estimation' [patent_app_type] => utility [patent_app_number] => 13/009467 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6783 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009467
DSP design system level power estimation Jan 18, 2011 Issued
Array ( [id] => 6167151 [patent_doc_number] => 20110161905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Layout Electromagnetic Extraction For High-Frequency Design And Verification' [patent_app_type] => utility [patent_app_number] => 12/983881 [patent_app_country] => US [patent_app_date] => 2011-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161905.pdf [firstpage_image] =>[orig_patent_app_number] => 12983881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983881
Layout Electromagnetic Extraction For High-Frequency Design And Verification Jan 2, 2011 Abandoned
Array ( [id] => 9278284 [patent_doc_number] => 20140028252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'POWER TRANSFER' [patent_app_type] => utility [patent_app_number] => 13/976224 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5440 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/976224
Power transfer Dec 30, 2010 Issued
Array ( [id] => 9218559 [patent_doc_number] => 08631369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-14 [patent_title] => 'Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations' [patent_app_type] => utility [patent_app_number] => 12/981504 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9130 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981504 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981504
Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations Dec 29, 2010 Issued
Array ( [id] => 9404885 [patent_doc_number] => 08694950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness' [patent_app_type] => utility [patent_app_number] => 12/982721 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8278 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12982721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982721
Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness Dec 29, 2010 Issued
Array ( [id] => 9089550 [patent_doc_number] => 08560998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Method, system, and program product to implement C-routing for double pattern lithography' [patent_app_type] => utility [patent_app_number] => 12/981431 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8666 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981431 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981431
Method, system, and program product to implement C-routing for double pattern lithography Dec 28, 2010 Issued
Array ( [id] => 6067797 [patent_doc_number] => 20110202892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'RETARGET PROCESS MODELING METHOD, METHOD OF FABRICATING MASK USING THE RETARGET PROCESS MODELING METHOD, COMPUTER READABLE STORAGE MEDIUM, AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/974681 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5873 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20110202892.pdf [firstpage_image] =>[orig_patent_app_number] => 12974681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974681
RETARGET PROCESS MODELING METHOD, METHOD OF FABRICATING MASK USING THE RETARGET PROCESS MODELING METHOD, COMPUTER READABLE STORAGE MEDIUM, AND IMAGING SYSTEM Dec 20, 2010 Abandoned
Array ( [id] => 10042467 [patent_doc_number] => 09083184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Battery pack for electric power tool, and battery connection device' [patent_app_type] => utility [patent_app_number] => 13/513445 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8834 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13513445 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/513445
Battery pack for electric power tool, and battery connection device Dec 16, 2010 Issued
Array ( [id] => 9315094 [patent_doc_number] => 08656330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software' [patent_app_type] => utility [patent_app_number] => 12/970851 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11484 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970851
Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software Dec 15, 2010 Issued
Array ( [id] => 8241739 [patent_doc_number] => 20120150479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'Debug Access with Programmable Return Clock' [patent_app_type] => utility [patent_app_number] => 12/965281 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12965281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965281
Debug access with programmable return clock Dec 9, 2010 Issued
Array ( [id] => 9404882 [patent_doc_number] => 08694947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Resource sharing workflows within executable graphical models' [patent_app_type] => utility [patent_app_number] => 12/963371 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 17986 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963371
Resource sharing workflows within executable graphical models Dec 7, 2010 Issued
Array ( [id] => 8946086 [patent_doc_number] => 08499273 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Systems and methods for optimizing placement and routing' [patent_app_type] => utility [patent_app_number] => 12/955521 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 9947 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12955521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955521
Systems and methods for optimizing placement and routing Nov 28, 2010 Issued
Array ( [id] => 8214307 [patent_doc_number] => 20120131528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/953661 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16355 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131528.pdf [firstpage_image] =>[orig_patent_app_number] => 12953661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953661
Method and apparatus for achieving multiple patterning technology compliant design layout Nov 23, 2010 Issued
Array ( [id] => 7504020 [patent_doc_number] => 20110265054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Design-Rule-Check Waiver' [patent_app_type] => utility [patent_app_number] => 12/954601 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8472 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265054.pdf [firstpage_image] =>[orig_patent_app_number] => 12954601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/954601
Design-Rule-Check Waiver Nov 23, 2010 Abandoned
Array ( [id] => 8212822 [patent_doc_number] => 20120130680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'System and method for capacity planning for systems with multithreaded multicore multiprocessor resources' [patent_app_type] => utility [patent_app_number] => 12/927761 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9557 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20120130680.pdf [firstpage_image] =>[orig_patent_app_number] => 12927761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/927761
System and method for capacity planning for systems with multithreaded multicore multiprocessor resources Nov 21, 2010 Issued
Array ( [id] => 8214291 [patent_doc_number] => 20120131523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/950371 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5547 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131523.pdf [firstpage_image] =>[orig_patent_app_number] => 12950371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950371
Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design Nov 18, 2010 Issued
Array ( [id] => 10080233 [patent_doc_number] => 09118092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Cooling arrangement for at least one battery in a vehicle' [patent_app_type] => utility [patent_app_number] => 13/510072 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4323 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13510072 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/510072
Cooling arrangement for at least one battery in a vehicle Nov 17, 2010 Issued
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