Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9579037 [patent_doc_number] => 08769474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-01 [patent_title] => 'Fast pattern matching' [patent_app_type] => utility [patent_app_number] => 12/907003 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12907003 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/907003
Fast pattern matching Oct 17, 2010 Issued
Array ( [id] => 9236108 [patent_doc_number] => 08601424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers' [patent_app_type] => utility [patent_app_number] => 12/893904 [patent_app_country] => US [patent_app_date] => 2010-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12893904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/893904
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Sep 28, 2010 Issued
Array ( [id] => 9130350 [patent_doc_number] => 08578307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Control/monitor automation for ASICs and programmable logic' [patent_app_type] => utility [patent_app_number] => 12/883581 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10189 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12883581 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883581
Control/monitor automation for ASICs and programmable logic Sep 15, 2010 Issued
Array ( [id] => 8810449 [patent_doc_number] => 08448116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Analog/digital partitioning of circuit designs for simulation' [patent_app_type] => utility [patent_app_number] => 12/873162 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7036 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12873162 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873162
Analog/digital partitioning of circuit designs for simulation Aug 30, 2010 Issued
Array ( [id] => 9379124 [patent_doc_number] => 08683411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Electronic design automation object placement with partially region-constrained objects' [patent_app_type] => utility [patent_app_number] => 12/870624 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6818 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12870624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/870624
Electronic design automation object placement with partially region-constrained objects Aug 26, 2010 Issued
Array ( [id] => 10162058 [patent_doc_number] => 09193272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Jump-starting method and device for implementing the method' [patent_app_type] => utility [patent_app_number] => 13/392456 [patent_app_country] => US [patent_app_date] => 2010-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13392456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/392456
Jump-starting method and device for implementing the method Aug 11, 2010 Issued
Array ( [id] => 8728517 [patent_doc_number] => 08407659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Method of designing a printed circuit board' [patent_app_type] => utility [patent_app_number] => 12/829921 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7057 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12829921 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829921
Method of designing a printed circuit board Jul 1, 2010 Issued
Array ( [id] => 9486680 [patent_doc_number] => 08732643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Support method, design support apparatus, computer product using combination pattern is prepared in advance' [patent_app_type] => utility [patent_app_number] => 12/817619 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6525 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12817619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817619
Support method, design support apparatus, computer product using combination pattern is prepared in advance Jun 16, 2010 Issued
Array ( [id] => 8170983 [patent_doc_number] => 08176447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Formation of masks/reticles having dummy features' [patent_app_type] => utility [patent_app_number] => 12/791942 [patent_app_country] => US [patent_app_date] => 2010-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3926 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176447.pdf [firstpage_image] =>[orig_patent_app_number] => 12791942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791942
Formation of masks/reticles having dummy features Jun 1, 2010 Issued
Array ( [id] => 9023649 [patent_doc_number] => 08533648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Automatic clock-gating propagation technique' [patent_app_type] => utility [patent_app_number] => 12/779891 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12779891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779891
Automatic clock-gating propagation technique May 12, 2010 Issued
Array ( [id] => 6566156 [patent_doc_number] => 20100223589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/776933 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6652 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223589.pdf [firstpage_image] =>[orig_patent_app_number] => 12776933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776933
Combination of ground devices in wiring harness designs May 9, 2010 Issued
Array ( [id] => 6537310 [patent_doc_number] => 20100287521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'MASK CREATION WITH HIERARCHY MANAGEMENT USING COVER CELLS' [patent_app_type] => utility [patent_app_number] => 12/776981 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4181 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20100287521.pdf [firstpage_image] =>[orig_patent_app_number] => 12776981 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776981
Mask creation with hierarchy management using cover cells May 9, 2010 Issued
Array ( [id] => 10834870 [patent_doc_number] => 08863065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Stacked die network-on-chip for FPGA' [patent_app_type] => utility [patent_app_number] => 12/775363 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7247 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12775363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775363
Stacked die network-on-chip for FPGA May 5, 2010 Issued
Array ( [id] => 9352474 [patent_doc_number] => 08671378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Method and system for distributing clock signals on non manhattan semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/772967 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 5510 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12772967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772967
Method and system for distributing clock signals on non manhattan semiconductor integrated circuits May 2, 2010 Issued
Array ( [id] => 8693335 [patent_doc_number] => 08392871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Decomposition with multiple exposures in a process window based OPC flow using tolerance bands' [patent_app_type] => utility [patent_app_number] => 12/770791 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 44 [patent_no_of_words] => 6832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12770791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/770791
Decomposition with multiple exposures in a process window based OPC flow using tolerance bands Apr 29, 2010 Issued
Array ( [id] => 7504017 [patent_doc_number] => 20110265052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'EFFICIENTLY APPLYING A SINGLE TIMING ASSERTION TO MULTIPLE TIMING POINTS IN A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/768031 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265052.pdf [firstpage_image] =>[orig_patent_app_number] => 12768031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768031
Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition Apr 26, 2010 Issued
Array ( [id] => 6596254 [patent_doc_number] => 20100275172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'RULE CHECK SYSTEM, DESIGN RULE CHECK METHOD AND DESIGN RULE CHECK PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/764481 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3227 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275172.pdf [firstpage_image] =>[orig_patent_app_number] => 12764481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764481
Rule check system, design rule check method and design rule check program Apr 20, 2010 Issued
Array ( [id] => 7504023 [patent_doc_number] => 20110265057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Method and Algorithm Analyzer for Determining a Design Framework' [patent_app_type] => utility [patent_app_number] => 12/764781 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6029 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265057.pdf [firstpage_image] =>[orig_patent_app_number] => 12764781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764781
Method and algorithm analyzer for determining a design framework Apr 20, 2010 Issued
Array ( [id] => 8703962 [patent_doc_number] => 08397199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Versatile method and tool for simulation of aged transistors' [patent_app_type] => utility [patent_app_number] => 12/762861 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12762861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762861
Versatile method and tool for simulation of aged transistors Apr 18, 2010 Issued
Array ( [id] => 6553559 [patent_doc_number] => 20100205343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Generating interface adjustment signals in a device-to-device interconnection system' [patent_app_type] => utility [patent_app_number] => 12/798971 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205343.pdf [firstpage_image] =>[orig_patent_app_number] => 12798971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/798971
Generating interface adjustment signals in a device-to-device interconnection system Apr 14, 2010 Issued
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