Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6312854 [patent_doc_number] => 20100194439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/758072 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 20932 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20100194439.pdf [firstpage_image] =>[orig_patent_app_number] => 12758072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758072
Logic circuit and method of logic circuit design Apr 11, 2010 Issued
Array ( [id] => 8971874 [patent_doc_number] => 08510704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Integrated circuit design system and method' [patent_app_type] => utility [patent_app_number] => 12/755311 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4147 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12755311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/755311
Integrated circuit design system and method Apr 5, 2010 Issued
Array ( [id] => 8504727 [patent_doc_number] => 20120304135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'METHOD AND APPARATUS FOR PRECISION TUNABLE MACRO-MODEL POWER ANALYSIS' [patent_app_type] => utility [patent_app_number] => 13/576101 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7836 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13576101 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/576101
METHOD AND APPARATUS FOR PRECISION TUNABLE MACRO-MODEL POWER ANALYSIS Mar 30, 2010 Abandoned
Array ( [id] => 8472860 [patent_doc_number] => 08302053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Automated integrated circuit clock insertion' [patent_app_type] => utility [patent_app_number] => 12/711651 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12711651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711651
Automated integrated circuit clock insertion Feb 23, 2010 Issued
Array ( [id] => 8633034 [patent_doc_number] => 08365133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Testing apparatus, testing method, and program' [patent_app_type] => utility [patent_app_number] => 12/710581 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8682 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710581 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710581
Testing apparatus, testing method, and program Feb 22, 2010 Issued
Array ( [id] => 9458726 [patent_doc_number] => 08719753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Stacked die network-on-chip for FPGA' [patent_app_type] => utility [patent_app_number] => 12/703681 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7200 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703681
Stacked die network-on-chip for FPGA Feb 9, 2010 Issued
Array ( [id] => 9218569 [patent_doc_number] => 08631379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Decomposing integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 12/702591 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8914 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12702591 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702591
Decomposing integrated circuit layout Feb 8, 2010 Issued
Array ( [id] => 8703946 [patent_doc_number] => 08397183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Generation of asymmetric circuit devices' [patent_app_type] => utility [patent_app_number] => 12/699621 [patent_app_country] => US [patent_app_date] => 2010-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4863 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12699621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/699621
Generation of asymmetric circuit devices Feb 2, 2010 Issued
Array ( [id] => 6463885 [patent_doc_number] => 20100146257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Dynamic reconfiguration computer product, apparatus, and method' [patent_app_type] => utility [patent_app_number] => 12/656531 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146257.pdf [firstpage_image] =>[orig_patent_app_number] => 12656531 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656531
Dynamic reconfiguration computer product, apparatus, and method Feb 1, 2010 Issued
Array ( [id] => 8645776 [patent_doc_number] => 08370775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Determining a predicted soft error rate for an integrated circuit device design' [patent_app_type] => utility [patent_app_number] => 12/698351 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698351
Determining a predicted soft error rate for an integrated circuit device design Feb 1, 2010 Issued
Array ( [id] => 8558299 [patent_doc_number] => 08332786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-11 [patent_title] => 'High level system design using functional and object-oriented composition' [patent_app_type] => utility [patent_app_number] => 12/697881 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12697881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697881
High level system design using functional and object-oriented composition Jan 31, 2010 Issued
Array ( [id] => 6605699 [patent_doc_number] => 20100131458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'GENERATION OF AN EXTRACTED TIMING MODEL FILE' [patent_app_type] => utility [patent_app_number] => 12/695396 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20100131458.pdf [firstpage_image] =>[orig_patent_app_number] => 12695396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695396
Generation of an extracted timing model file Jan 27, 2010 Issued
Array ( [id] => 8799636 [patent_doc_number] => 08438525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/644001 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 5523 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644001 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644001
Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits Dec 20, 2009 Issued
Array ( [id] => 9923742 [patent_doc_number] => 08981712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Converter and submodule of a converter for charging or discharging an energy store' [patent_app_type] => utility [patent_app_number] => 13/510341 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13510341 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/510341
Converter and submodule of a converter for charging or discharging an energy store Nov 18, 2009 Issued
Array ( [id] => 6228051 [patent_doc_number] => 20100058278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'METHOD AND APPARATUS FOR AUTOMATED SYNTHESIS OF MULTI-CHANNEL CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/618683 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10102 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20100058278.pdf [firstpage_image] =>[orig_patent_app_number] => 12618683 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618683
Method and apparatus for automated synthesis of multi-channel circuits Nov 12, 2009 Issued
Array ( [id] => 8752244 [patent_doc_number] => 08418088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Methods and system for lithography calibration' [patent_app_type] => utility [patent_app_number] => 12/613221 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 19708 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12613221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613221
Methods and system for lithography calibration Nov 4, 2009 Issued
Array ( [id] => 9302273 [patent_doc_number] => 08650517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-11 [patent_title] => 'Automatically documenting circuit designs' [patent_app_type] => utility [patent_app_number] => 12/581631 [patent_app_country] => US [patent_app_date] => 2009-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12581631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/581631
Automatically documenting circuit designs Oct 18, 2009 Issued
Array ( [id] => 8752247 [patent_doc_number] => 08418091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Method and apparatus for camouflaging a standard cell based integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/578441 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 37 [patent_no_of_words] => 11368 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12578441 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578441
Method and apparatus for camouflaging a standard cell based integrated circuit Oct 12, 2009 Issued
Array ( [id] => 8530738 [patent_doc_number] => 08307322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Wiring design apparatus' [patent_app_type] => utility [patent_app_number] => 12/574071 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 38 [patent_no_of_words] => 9099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12574071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574071
Wiring design apparatus Oct 5, 2009 Issued
Array ( [id] => 6125931 [patent_doc_number] => 20110078641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Characterization of Long Range Variability' [patent_app_type] => utility [patent_app_number] => 12/569421 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078641.pdf [firstpage_image] =>[orig_patent_app_number] => 12569421 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569421
Characterization of long range variability Sep 28, 2009 Issued
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