Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6389498 [patent_doc_number] => 20100083196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'AUTOMATIC CIRCUIT DESIGN APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/565951 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13793 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083196.pdf [firstpage_image] =>[orig_patent_app_number] => 12565951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565951
Automatic circuit design apparatus and method Sep 23, 2009 Issued
Array ( [id] => 8401518 [patent_doc_number] => 08271913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Method and system for design and modeling of transmission lines' [patent_app_type] => utility [patent_app_number] => 12/564061 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5707 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12564061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564061
Method and system for design and modeling of transmission lines Sep 21, 2009 Issued
Array ( [id] => 6366207 [patent_doc_number] => 20100251192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'CIRCUIT DESCRIPTION GENERATING APPARATUS AND FUNCTION VERIFICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/563891 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251192.pdf [firstpage_image] =>[orig_patent_app_number] => 12563891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563891
CIRCUIT DESCRIPTION GENERATING APPARATUS AND FUNCTION VERIFICATION METHOD Sep 20, 2009 Abandoned
Array ( [id] => 8412693 [patent_doc_number] => 08276105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Automatic positioning of gate array circuits in an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/563021 [patent_app_country] => US [patent_app_date] => 2009-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 11776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12563021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563021
Automatic positioning of gate array circuits in an integrated circuit design Sep 17, 2009 Issued
Array ( [id] => 6204211 [patent_doc_number] => 20110066997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'MODELING AND SIMULATING DEVICE MISMATCH FOR DESIGNING INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/561801 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7724 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066997.pdf [firstpage_image] =>[orig_patent_app_number] => 12561801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561801
Modeling and simulating device mismatch for designing integrated circuits Sep 16, 2009 Issued
Array ( [id] => 7813546 [patent_doc_number] => 08136084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Arranging through silicon vias in IC layout' [patent_app_type] => utility [patent_app_number] => 12/555981 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136084.pdf [firstpage_image] =>[orig_patent_app_number] => 12555981 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555981
Arranging through silicon vias in IC layout Sep 8, 2009 Issued
Array ( [id] => 6389603 [patent_doc_number] => 20100083214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'DESIGN DESCRIPTION REWRITING DEVICE, DESIGN DESCRIPTION REWRITING METHOD, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/554351 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7130 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083214.pdf [firstpage_image] =>[orig_patent_app_number] => 12554351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554351
Description rewriting device, design description rewriting method, and computer readable medium Sep 3, 2009 Issued
Array ( [id] => 6621653 [patent_doc_number] => 20100064272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'System and method for supporting layout design of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/585121 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8716 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064272.pdf [firstpage_image] =>[orig_patent_app_number] => 12585121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585121
System and method for supporting layout design of semiconductor integrated circuit Sep 2, 2009 Issued
Array ( [id] => 8022985 [patent_doc_number] => 08141012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Timing closure on multiple selective corners in a single statistical timing run' [patent_app_type] => utility [patent_app_number] => 12/549061 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5880 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141012.pdf [firstpage_image] =>[orig_patent_app_number] => 12549061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549061
Timing closure on multiple selective corners in a single statistical timing run Aug 26, 2009 Issued
Array ( [id] => 8366764 [patent_doc_number] => 08255846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Development tool for comparing netlists' [patent_app_type] => utility [patent_app_number] => 12/543301 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12543301 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543301
Development tool for comparing netlists Aug 17, 2009 Issued
Array ( [id] => 7680910 [patent_doc_number] => 20100023898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'CIRCUIT DESIGN ASSISTING APPARATUS, COMPUTER-READABLE MEDIUM STORING CIRCUIT DESIGN ASSISTING PROGRAM, AND CIRCUIT DESIGN ASSISTING METHOD' [patent_app_type] => utility [patent_app_number] => 12/507411 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5743 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023898.pdf [firstpage_image] =>[orig_patent_app_number] => 12507411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507411
Circuit design assisting apparatus, computer-readable medium storing circuit design assisting program, and circuit design assisting method Jul 21, 2009 Issued
Array ( [id] => 7537750 [patent_doc_number] => 08051393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Gate modeling for semiconductor fabrication process effects' [patent_app_type] => utility [patent_app_number] => 12/502922 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051393.pdf [firstpage_image] =>[orig_patent_app_number] => 12502922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502922
Gate modeling for semiconductor fabrication process effects Jul 13, 2009 Issued
Array ( [id] => 8120421 [patent_doc_number] => 08161433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Utilizing an unSAT proof for model checking' [patent_app_type] => utility [patent_app_number] => 12/501501 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11387 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161433.pdf [firstpage_image] =>[orig_patent_app_number] => 12501501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501501
Utilizing an unSAT proof for model checking Jul 12, 2009 Issued
Array ( [id] => 8389153 [patent_doc_number] => 08266558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Methods for forming arrays of small, closely spaced features' [patent_app_type] => utility [patent_app_number] => 12/498951 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 45 [patent_no_of_words] => 12096 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12498951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498951
Methods for forming arrays of small, closely spaced features Jul 6, 2009 Issued
Array ( [id] => 5493825 [patent_doc_number] => 20090261853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Semiconductor device and method of testing the same' [patent_app_type] => utility [patent_app_number] => 12/492957 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8131 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20090261853.pdf [firstpage_image] =>[orig_patent_app_number] => 12492957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492957
Semiconductor device and method of testing the same Jun 25, 2009 Issued
Array ( [id] => 8033911 [patent_doc_number] => 08146050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Graphical program with physical simulation and data flow portions' [patent_app_type] => utility [patent_app_number] => 12/485174 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 14301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146050.pdf [firstpage_image] =>[orig_patent_app_number] => 12485174 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/485174
Graphical program with physical simulation and data flow portions Jun 15, 2009 Issued
Array ( [id] => 5491961 [patent_doc_number] => 20090293032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'METHOD AND APPARATUS FOR CIRCUIT DESIGN AND RETIMING' [patent_app_type] => utility [patent_app_number] => 12/432446 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10995 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20090293032.pdf [firstpage_image] =>[orig_patent_app_number] => 12432446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432446
Circuit design and retiming Apr 28, 2009 Issued
Array ( [id] => 7746703 [patent_doc_number] => 08108824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Pattern verification method, method of manufacturing semiconductor device, and recording media' [patent_app_type] => utility [patent_app_number] => 12/420931 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108824.pdf [firstpage_image] =>[orig_patent_app_number] => 12420931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/420931
Pattern verification method, method of manufacturing semiconductor device, and recording media Apr 8, 2009 Issued
Array ( [id] => 6366262 [patent_doc_number] => 20100251198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/415266 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251198.pdf [firstpage_image] =>[orig_patent_app_number] => 12415266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/415266
Method for extracting information for a circuit design Mar 30, 2009 Issued
Array ( [id] => 9472564 [patent_doc_number] => 08726213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Method and apparatus for decomposing functions in a configurable IC' [patent_app_type] => utility [patent_app_number] => 12/414660 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 51 [patent_no_of_words] => 18463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12414660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414660
Method and apparatus for decomposing functions in a configurable IC Mar 29, 2009 Issued
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