Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6554685 [patent_doc_number] => 20100125822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING INTERACTIVE CROSS-DOMAIN PACKAGE DRIVEN I/O PLANNING AND PLACEMENT OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/414261 [patent_app_country] => US [patent_app_date] => 2009-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10250 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20100125822.pdf [firstpage_image] =>[orig_patent_app_number] => 12414261 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414261
Methods, systems, and computer program product for implementing interactive cross-domain package driven I/O planning and placement optimization Mar 29, 2009 Issued
Array ( [id] => 8011135 [patent_doc_number] => 08086986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-27 [patent_title] => 'Clock boosting systems and methods' [patent_app_type] => utility [patent_app_number] => 12/408047 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4650 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086986.pdf [firstpage_image] =>[orig_patent_app_number] => 12408047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/408047
Clock boosting systems and methods Mar 19, 2009 Issued
Array ( [id] => 8273267 [patent_doc_number] => 08214790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Low RC global clock distribution' [patent_app_type] => utility [patent_app_number] => 12/397941 [patent_app_country] => US [patent_app_date] => 2009-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5935 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12397941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397941
Low RC global clock distribution Mar 3, 2009 Issued
Array ( [id] => 6652459 [patent_doc_number] => 20100229145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Use Of Graphs To Decompose Layout Design Data' [patent_app_type] => utility [patent_app_number] => 12/397321 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8963 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229145.pdf [firstpage_image] =>[orig_patent_app_number] => 12397321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397321
Use of graphs to decompose layout design data Mar 2, 2009 Issued
Array ( [id] => 5516926 [patent_doc_number] => 20090217233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'SIMULATION METHOD AND SIMULATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/395481 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7139 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217233.pdf [firstpage_image] =>[orig_patent_app_number] => 12395481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/395481
Simulation method and simulation program Feb 26, 2009 Issued
Array ( [id] => 8285835 [patent_doc_number] => 08219952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Variation aware victim and aggressor timing overlap detection by pessimism reduction based on relative positions of timing windows' [patent_app_type] => utility [patent_app_number] => 12/391241 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 11228 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12391241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/391241
Variation aware victim and aggressor timing overlap detection by pessimism reduction based on relative positions of timing windows Feb 22, 2009 Issued
Array ( [id] => 5512514 [patent_doc_number] => 20090212818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Integrated circuit design method for improved testability' [patent_app_type] => utility [patent_app_number] => 12/379411 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7169 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212818.pdf [firstpage_image] =>[orig_patent_app_number] => 12379411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379411
Integrated circuit design method for improved testability Feb 19, 2009 Abandoned
Array ( [id] => 5470235 [patent_doc_number] => 20090243401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'SEMICONDUCTOR DEVICE USING A PLURALITY OF HIGH-POTENTIAL-SIDE REFERENCE VOLTAGES' [patent_app_type] => utility [patent_app_number] => 12/371071 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243401.pdf [firstpage_image] =>[orig_patent_app_number] => 12371071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371071
Semiconductor device using a plurality of high-potential-side reference voltages Feb 12, 2009 Issued
Array ( [id] => 6302835 [patent_doc_number] => 20100162184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'High Speed Reduced Area Cell Library With Cells Having Integer Multiple Track Heights' [patent_app_type] => utility [patent_app_number] => 12/370051 [patent_app_country] => US [patent_app_date] => 2009-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7772 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162184.pdf [firstpage_image] =>[orig_patent_app_number] => 12370051 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/370051
High speed reduced area cell library with cells having integer multiple track heights Feb 11, 2009 Issued
Array ( [id] => 6557291 [patent_doc_number] => 20100205576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SYSTEM AND METHOD FOR APERTURE BASED LAYOUT DATA ANALYSIS TO ACHIEVE NEIGHBORHOOD AWARENESS' [patent_app_type] => utility [patent_app_number] => 12/366911 [patent_app_country] => US [patent_app_date] => 2009-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7249 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205576.pdf [firstpage_image] =>[orig_patent_app_number] => 12366911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/366911
System and method for aperture based layout data analysis to achieve neighborhood awareness Feb 5, 2009 Issued
Array ( [id] => 8022983 [patent_doc_number] => 08141011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-20 [patent_title] => 'Hardware description language code generation from a state diagram' [patent_app_type] => utility [patent_app_number] => 12/360558 [patent_app_country] => US [patent_app_date] => 2009-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8932 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141011.pdf [firstpage_image] =>[orig_patent_app_number] => 12360558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/360558
Hardware description language code generation from a state diagram Jan 26, 2009 Issued
Array ( [id] => 5565987 [patent_doc_number] => 20090138840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'CELL, STANDARD CELL, STANDARD CELL LIBRARY, A PLACEMENT METHOD USING STANDARD CELL, AND A SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/359615 [patent_app_country] => US [patent_app_date] => 2009-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11332 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138840.pdf [firstpage_image] =>[orig_patent_app_number] => 12359615 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359615
CELL, STANDARD CELL, STANDARD CELL LIBRARY, A PLACEMENT METHOD USING STANDARD CELL, AND A SEMICONDUCTOR INTEGRATED CIRCUIT Jan 25, 2009 Abandoned
Array ( [id] => 5438047 [patent_doc_number] => 20090172634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'INTERACTIVE LOOP CONFIGURATION IN A BEHAVIORAL SYNTHESIS TOOL' [patent_app_type] => utility [patent_app_number] => 12/353210 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172634.pdf [firstpage_image] =>[orig_patent_app_number] => 12353210 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/353210
Interactive loop configuration in a behavioral synthesis tool Jan 12, 2009 Issued
Array ( [id] => 8022999 [patent_doc_number] => 08141019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Method for optimizing of pipeline structure placement' [patent_app_type] => utility [patent_app_number] => 12/348380 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4424 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141019.pdf [firstpage_image] =>[orig_patent_app_number] => 12348380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348380
Method for optimizing of pipeline structure placement Jan 4, 2009 Issued
Array ( [id] => 5587519 [patent_doc_number] => 20090106721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH FAULT DETECTION CAN BE EFFECTED THROUGH SCAN-IN AND SCAN-OUT' [patent_app_type] => utility [patent_app_number] => 12/334988 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 26149 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106721.pdf [firstpage_image] =>[orig_patent_app_number] => 12334988 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334988
METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT IN WHICH FAULT DETECTION CAN BE EFFECTED THROUGH SCAN-IN AND SCAN-OUT Dec 14, 2008 Abandoned
Array ( [id] => 5442924 [patent_doc_number] => 20090094563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Method and System for Enhanced Verification By Closely Coupling a Structural Satisfiability Solver and Rewriting Algorithms' [patent_app_type] => utility [patent_app_number] => 12/332191 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094563.pdf [firstpage_image] =>[orig_patent_app_number] => 12332191 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332191
Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms Dec 9, 2008 Issued
Array ( [id] => 7993401 [patent_doc_number] => 08079009 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Managing interrupt requests from IP cores' [patent_app_type] => utility [patent_app_number] => 12/329881 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/079/08079009.pdf [firstpage_image] =>[orig_patent_app_number] => 12329881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329881
Managing interrupt requests from IP cores Dec 7, 2008 Issued
Array ( [id] => 5353414 [patent_doc_number] => 20090184758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Semiconductor integrated circuit and switch arranging and wiring method apparatus' [patent_app_type] => utility [patent_app_number] => 12/314111 [patent_app_country] => US [patent_app_date] => 2008-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20090184758.pdf [firstpage_image] =>[orig_patent_app_number] => 12314111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314111
Semiconductor integrated circuit and switch arranging and wiring method Dec 3, 2008 Issued
Array ( [id] => 8297464 [patent_doc_number] => 08225265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Logic circuit delay optimization' [patent_app_type] => utility [patent_app_number] => 12/292931 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 12022 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12292931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292931
Logic circuit delay optimization Nov 30, 2008 Issued
Array ( [id] => 8183371 [patent_doc_number] => 08181146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'Equivalence checker' [patent_app_type] => utility [patent_app_number] => 12/277131 [patent_app_country] => US [patent_app_date] => 2008-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3257 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181146.pdf [firstpage_image] =>[orig_patent_app_number] => 12277131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/277131
Equivalence checker Nov 23, 2008 Issued
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