Jeffrey T. Knapp

Array ( [id] => 8033863 [patent_doc_number] => 08146028 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Duplicate design flow for mitigation of soft errors in IC operation' [patent_app_type] => utility [patent_app_number] => 12/274261 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5186 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146028.pdf [firstpage_image] =>[orig_patent_app_number] => 12274261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6332813 [patent_doc_number] => 20100115484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Standard cell placement' [patent_app_type] => utility [patent_app_number] => 12/289771 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6959 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20100115484.pdf [firstpage_image] =>[orig_patent_app_number] => 12289771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7768444 [patent_doc_number] => 08117571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-14 [patent_title] => 'System, method, and computer program product for determining equivalence of netlists utilizing abstractions and transformations' [patent_app_type] => utility [patent_app_number] => 12/260851 [patent_app_country] => US [patent_app_date] => 2008-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7950 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117571.pdf [firstpage_image] =>[orig_patent_app_number] => 12260851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7813540 [patent_doc_number] => 08136078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Optimization' [patent_app_type] => utility [patent_app_number] => 12/258261 [patent_app_country] => US [patent_app_date] => 2008-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7634 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136078.pdf [firstpage_image] =>[orig_patent_app_number] => 12258261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5454688 [patent_doc_number] => 20090070725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Method and system for manufacturing a semiconductor device having plural wiring layers' [patent_app_type] => utility [patent_app_number] => 12/289296 [patent_app_country] => US [patent_app_date] => 2008-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070725.pdf [firstpage_image] =>[orig_patent_app_number] => 12289296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10524788 [patent_doc_number] => 09251305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-02 [patent_title] => 'Method and apparatus for analyzing structured cell candidates for structured application specific integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/287993 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4830 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12287993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6513186 [patent_doc_number] => 20100095264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'METHOD AND APPARATUS FOR DETERMINING A PHOTOLITHOGRAPHY PROCESS MODEL WHICH MODELS THE INFLUENCE OF TOPOGRAPHY VARIATIONS' [patent_app_type] => utility [patent_app_number] => 12/250391 [patent_app_country] => US [patent_app_date] => 2008-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20100095264.pdf [firstpage_image] =>[orig_patent_app_number] => 12250391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5438043 [patent_doc_number] => 20090172630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/248883 [patent_app_country] => US [patent_app_date] => 2008-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 28309 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172630.pdf [firstpage_image] =>[orig_patent_app_number] => 12248883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8120429 [patent_doc_number] => 08161432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Automated processor generation system and method for designing a configurable processor' [patent_app_type] => utility [patent_app_number] => 12/248890 [patent_app_country] => US [patent_app_date] => 2008-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 28180 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161432.pdf [firstpage_image] =>[orig_patent_app_number] => 12248890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8366761 [patent_doc_number] => 08255842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device' [patent_app_type] => utility [patent_app_number] => 12/246831 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 8183 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12246831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8109615 [patent_doc_number] => 08156462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Verification technique including deriving invariants from constraints' [patent_app_type] => utility [patent_app_number] => 12/243821 [patent_app_country] => US [patent_app_date] => 2008-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4334 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156462.pdf [firstpage_image] =>[orig_patent_app_number] => 12243821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8149408 [patent_doc_number] => 08166425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Validating circuit simulation results' [patent_app_type] => utility [patent_app_number] => 12/238880 [patent_app_country] => US [patent_app_date] => 2008-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166425.pdf [firstpage_image] =>[orig_patent_app_number] => 12238880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326357 [patent_doc_number] => 08661394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Depth-optimal mapping of logic chains in reconfigurable fabrics' [patent_app_type] => utility [patent_app_number] => 12/236781 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12236781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187251 [patent_doc_number] => 08627252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Method for selectively implementing low threshold voltage transistors in digital logic designs' [patent_app_type] => utility [patent_app_number] => 12/233191 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12233191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6621666 [patent_doc_number] => 20100064273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Method for Compensating for Variations in Structures of an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/208521 [patent_app_country] => US [patent_app_date] => 2008-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20100064273.pdf [firstpage_image] =>[orig_patent_app_number] => 12208521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5273750 [patent_doc_number] => 20090077526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Write-Pattern Determination for Maskless Lithography' [patent_app_type] => utility [patent_app_number] => 12/206651 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7793 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077526.pdf [firstpage_image] =>[orig_patent_app_number] => 12206651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8022993 [patent_doc_number] => 08141016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Integrated design for manufacturing for 1×N VLSI design' [patent_app_type] => utility [patent_app_number] => 12/201591 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 18409 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141016.pdf [firstpage_image] =>[orig_patent_app_number] => 12201591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5326095 [patent_doc_number] => 20090064085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'METHOD OF CREATING PHOTO MASK LAYOUT, COMPUTER READABLE RECORDING MEDIUM STORING PROGRAMMED INSTRUCTIONS FOR EXECUTING THE METHOD, AND MASK IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/201701 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20090064085.pdf [firstpage_image] =>[orig_patent_app_number] => 12201701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9404868 [patent_doc_number] => 08694932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Layout determination' [patent_app_type] => utility [patent_app_number] => 12/200271 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5746 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12200271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7780242 [patent_doc_number] => 08122399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Compiler for closed-loop 1×N VLSI design' [patent_app_type] => utility [patent_app_number] => 12/200121 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 16562 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122399.pdf [firstpage_image] =>[orig_patent_app_number] => 12200121 [rel_patent_id] =>[rel_patent_doc_number] =>)