
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4626907
[patent_doc_number] => 08006219
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[patent_issue_date] => 2011-08-23
[patent_title] => 'Wiring path information creating method and wiring path information creating apparatus'
[patent_app_type] => utility
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[patent_app_date] => 2008-08-13
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[pdf_file] => patents/08/006/08006219.pdf
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Array
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[patent_issue_date] => 2012-08-28
[patent_title] => 'DC path checking in a hierarchical circuit design'
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[patent_app_date] => 2008-08-11
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Array
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[patent_issue_date] => 2008-12-11
[patent_title] => 'Method for Performing Timing Analysis of a Circuit'
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[patent_app_date] => 2008-08-05
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Array
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[patent_issue_date] => 2011-11-22
[patent_title] => 'Techniques for use with automated circuit design and simulations'
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[patent_app_date] => 2008-07-25
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Array
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Array
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Array
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[patent_title] => 'Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same'
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Array
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[patent_title] => 'Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit'
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[patent_title] => 'METHOD OF CREATING MASK LAYOUT IMAGE AND IMAGING SYSTEM'
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Array
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[patent_title] => 'Display designing system and method for designing a display'
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Array
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Array
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