Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4626907 [patent_doc_number] => 08006219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Wiring path information creating method and wiring path information creating apparatus' [patent_app_type] => utility [patent_app_number] => 12/222661 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6077 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006219.pdf [firstpage_image] =>[orig_patent_app_number] => 12222661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222661
Wiring path information creating method and wiring path information creating apparatus Aug 12, 2008 Issued
Array ( [id] => 8366779 [patent_doc_number] => 08255856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'DC path checking in a hierarchical circuit design' [patent_app_type] => utility [patent_app_number] => 12/189645 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 13018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12189645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/189645
DC path checking in a hierarchical circuit design Aug 10, 2008 Issued
Array ( [id] => 4951249 [patent_doc_number] => 20080307375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Method for Performing Timing Analysis of a Circuit' [patent_app_type] => utility [patent_app_number] => 12/186431 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11872 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307375.pdf [firstpage_image] =>[orig_patent_app_number] => 12186431 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186431
Method for performing timing analysis of a circuit Aug 4, 2008 Issued
Array ( [id] => 7553308 [patent_doc_number] => 08065650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Techniques for use with automated circuit design and simulations' [patent_app_type] => utility [patent_app_number] => 12/180448 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065650.pdf [firstpage_image] =>[orig_patent_app_number] => 12180448 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180448
Techniques for use with automated circuit design and simulations Jul 24, 2008 Issued
Array ( [id] => 5288120 [patent_doc_number] => 20090020850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/174921 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4092 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20090020850.pdf [firstpage_image] =>[orig_patent_app_number] => 12174921 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174921
SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD Jul 16, 2008 Abandoned
Array ( [id] => 7706546 [patent_doc_number] => 08091062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Logic circuits having dynamically configurable logic gate arrays' [patent_app_type] => utility [patent_app_number] => 12/174332 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3658 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091062.pdf [firstpage_image] =>[orig_patent_app_number] => 12174332 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174332
Logic circuits having dynamically configurable logic gate arrays Jul 15, 2008 Issued
Array ( [id] => 7510735 [patent_doc_number] => 08037446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same' [patent_app_type] => utility [patent_app_number] => 12/174171 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5043 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037446.pdf [firstpage_image] =>[orig_patent_app_number] => 12174171 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174171
Methods for defining evaluation points for optical proximity correction and optical proximity correction methods including same Jul 15, 2008 Issued
Array ( [id] => 5523286 [patent_doc_number] => 20090031267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/219021 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4128 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031267.pdf [firstpage_image] =>[orig_patent_app_number] => 12219021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219021
Layout correcting method for semiconductor integrated circuit and layout correcting device for semiconductor integrated circuit Jul 14, 2008 Abandoned
Array ( [id] => 5312123 [patent_doc_number] => 20090019404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'METHOD FOR CALCULATING DIFFICULTY LEVEL OF ROUTING IN NETLIST' [patent_app_type] => utility [patent_app_number] => 12/169481 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5986 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019404.pdf [firstpage_image] =>[orig_patent_app_number] => 12169481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169481
METHOD FOR CALCULATING DIFFICULTY LEVEL OF ROUTING IN NETLIST Jul 7, 2008 Abandoned
Array ( [id] => 5298377 [patent_doc_number] => 20090013303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'METHOD OF CREATING MASK LAYOUT IMAGE AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/167411 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013303.pdf [firstpage_image] =>[orig_patent_app_number] => 12167411 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167411
METHOD OF CREATING MASK LAYOUT IMAGE AND IMAGING SYSTEM Jul 2, 2008 Abandoned
Array ( [id] => 4637050 [patent_doc_number] => 08015515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Display designing system and method for designing a display' [patent_app_type] => utility [patent_app_number] => 12/167521 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3558 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015515.pdf [firstpage_image] =>[orig_patent_app_number] => 12167521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167521
Display designing system and method for designing a display Jul 2, 2008 Issued
Array ( [id] => 325411 [patent_doc_number] => 07519927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-14 [patent_title] => 'Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations' [patent_app_type] => utility [patent_app_number] => 12/166561 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5752 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519927.pdf [firstpage_image] =>[orig_patent_app_number] => 12166561 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166561
Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations Jul 1, 2008 Issued
Array ( [id] => 7706548 [patent_doc_number] => 08091063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Method and apparatus for characterizing an integrated circuit manufacturing process' [patent_app_type] => utility [patent_app_number] => 12/166781 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4062 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091063.pdf [firstpage_image] =>[orig_patent_app_number] => 12166781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166781
Method and apparatus for characterizing an integrated circuit manufacturing process Jul 1, 2008 Issued
Array ( [id] => 5351684 [patent_doc_number] => 20090007045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD OF DESIGNING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/164391 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2789 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007045.pdf [firstpage_image] =>[orig_patent_app_number] => 12164391 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164391
Method of designing a semiconductor device Jun 29, 2008 Issued
Array ( [id] => 4614401 [patent_doc_number] => 07996808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Computer readable medium, system and associated method for designing integrated circuits with loop insertions' [patent_app_type] => utility [patent_app_number] => 12/146921 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4043 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996808.pdf [firstpage_image] =>[orig_patent_app_number] => 12146921 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146921
Computer readable medium, system and associated method for designing integrated circuits with loop insertions Jun 25, 2008 Issued
Array ( [id] => 4862659 [patent_doc_number] => 20080270967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing' [patent_app_type] => utility [patent_app_number] => 12/213623 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6685 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270967.pdf [firstpage_image] =>[orig_patent_app_number] => 12213623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213623
Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing Jun 22, 2008 Issued
Array ( [id] => 4958667 [patent_doc_number] => 20080273091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Buffering technique using structrured delay skewing' [patent_app_type] => utility [patent_app_number] => 12/213563 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273091.pdf [firstpage_image] =>[orig_patent_app_number] => 12213563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213563
Buffering technique using structured delay skewing Jun 19, 2008 Issued
Array ( [id] => 4889163 [patent_doc_number] => 20080263495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Software product for semiconductor device design' [patent_app_type] => utility [patent_app_number] => 12/213412 [patent_app_country] => US [patent_app_date] => 2008-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263495.pdf [firstpage_image] =>[orig_patent_app_number] => 12213412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213412
Software product for semiconductor device design Jun 18, 2008 Issued
Array ( [id] => 9532674 [patent_doc_number] => 08756560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Method for designing dummy pattern, exposure mask, semiconductor device, method for semiconductor device, and storage medium' [patent_app_type] => utility [patent_app_number] => 12/213371 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 7642 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12213371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213371
Method for designing dummy pattern, exposure mask, semiconductor device, method for semiconductor device, and storage medium Jun 17, 2008 Issued
Array ( [id] => 8023013 [patent_doc_number] => 08141026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-20 [patent_title] => 'Method and system for rapidly identifying silicon manufacturing defects' [patent_app_type] => utility [patent_app_number] => 12/138080 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3469 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141026.pdf [firstpage_image] =>[orig_patent_app_number] => 12138080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/138080
Method and system for rapidly identifying silicon manufacturing defects Jun 11, 2008 Issued
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