Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4741990 [patent_doc_number] => 20080235643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Method and system for reducing inter-layer capacitance in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/156281 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235643.pdf [firstpage_image] =>[orig_patent_app_number] => 12156281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/156281
Method and system for reducing inter-layer capacitance in integrated circuits May 29, 2008 Issued
Array ( [id] => 368910 [patent_doc_number] => 07480888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-20 [patent_title] => 'Design structure for facilitating engineering changes in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/124771 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3329 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480888.pdf [firstpage_image] =>[orig_patent_app_number] => 12124771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124771
Design structure for facilitating engineering changes in integrated circuits May 20, 2008 Issued
Array ( [id] => 4587349 [patent_doc_number] => 07849433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Integrated circuit with uniform polysilicon perimeter density, method and design structure' [patent_app_type] => utility [patent_app_number] => 12/117771 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5490 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849433.pdf [firstpage_image] =>[orig_patent_app_number] => 12117771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117771
Integrated circuit with uniform polysilicon perimeter density, method and design structure May 8, 2008 Issued
Array ( [id] => 4889162 [patent_doc_number] => 20080263494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Power supply wiring structure' [patent_app_type] => utility [patent_app_number] => 12/149891 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10713 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263494.pdf [firstpage_image] =>[orig_patent_app_number] => 12149891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149891
Power supply wiring structure May 8, 2008 Issued
Array ( [id] => 5317784 [patent_doc_number] => 20090282382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS' [patent_app_type] => utility [patent_app_number] => 12/115991 [patent_app_country] => US [patent_app_date] => 2008-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7176 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282382.pdf [firstpage_image] =>[orig_patent_app_number] => 12115991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115991
System and method for routing connections with improved interconnect thickness May 5, 2008 Issued
Array ( [id] => 9156923 [patent_doc_number] => 08589836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Formally checking equivalence using equivalence relationships' [patent_app_type] => utility [patent_app_number] => 12/112940 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 108 [patent_no_of_words] => 41467 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12112940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112940
Formally checking equivalence using equivalence relationships Apr 29, 2008 Issued
Array ( [id] => 4741600 [patent_doc_number] => 20080235253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD AND APPARATUS FOR FORMALLY CHECKING EQUIVALENCE USING EQUIVALENCE RELATIONSHIPS' [patent_app_type] => utility [patent_app_number] => 12/112996 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 84 [patent_no_of_words] => 41298 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235253.pdf [firstpage_image] =>[orig_patent_app_number] => 12112996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112996
Method and apparatus for formally checking equivalence using equivalence relationships Apr 29, 2008 Issued
Array ( [id] => 4730469 [patent_doc_number] => 20080209181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Method and System for Automatic Generation of Processor Datapaths' [patent_app_type] => utility [patent_app_number] => 12/111153 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9672 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209181.pdf [firstpage_image] =>[orig_patent_app_number] => 12111153 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111153
Method and system for automatic generation of processor datapaths Apr 27, 2008 Issued
Array ( [id] => 4500842 [patent_doc_number] => 07904866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Computer readable recording medium with a wiring design program stored thereon and wiring design device' [patent_app_type] => utility [patent_app_number] => 12/107911 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7030 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904866.pdf [firstpage_image] =>[orig_patent_app_number] => 12107911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107911
Computer readable recording medium with a wiring design program stored thereon and wiring design device Apr 22, 2008 Issued
Array ( [id] => 7780230 [patent_doc_number] => 08122393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Integrated circuit transformer devices for on-chip millimeter-wave applications' [patent_app_type] => utility [patent_app_number] => 12/106531 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6760 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122393.pdf [firstpage_image] =>[orig_patent_app_number] => 12106531 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/106531
Integrated circuit transformer devices for on-chip millimeter-wave applications Apr 20, 2008 Issued
Array ( [id] => 4614400 [patent_doc_number] => 07996807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method' [patent_app_type] => utility [patent_app_number] => 12/104461 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996807.pdf [firstpage_image] =>[orig_patent_app_number] => 12104461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104461
Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method Apr 16, 2008 Issued
Array ( [id] => 5497644 [patent_doc_number] => 20090265672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/103961 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2751 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265672.pdf [firstpage_image] =>[orig_patent_app_number] => 12103961 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/103961
Method and system for entry and verification of parasitic design constraints for analog integrated circuits Apr 15, 2008 Issued
Array ( [id] => 4441453 [patent_doc_number] => 07971164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Assessing resources required to complete a VLSI design' [patent_app_type] => utility [patent_app_number] => 12/100481 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971164.pdf [firstpage_image] =>[orig_patent_app_number] => 12100481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/100481
Assessing resources required to complete a VLSI design Apr 9, 2008 Issued
Array ( [id] => 4956639 [patent_doc_number] => 20080189663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS' [patent_app_type] => utility [patent_app_number] => 12/061155 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6651 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189663.pdf [firstpage_image] =>[orig_patent_app_number] => 12061155 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/061155
Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells Apr 1, 2008 Issued
Array ( [id] => 4513422 [patent_doc_number] => 07921395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Method for laying out decoupling cells and apparatus for laying out decoupling cells' [patent_app_type] => utility [patent_app_number] => 12/078341 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4301 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/921/07921395.pdf [firstpage_image] =>[orig_patent_app_number] => 12078341 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078341
Method for laying out decoupling cells and apparatus for laying out decoupling cells Mar 27, 2008 Issued
Array ( [id] => 4621768 [patent_doc_number] => 08001499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Circuit type pragma for computer aided design tools' [patent_app_type] => utility [patent_app_number] => 12/053481 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5725 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001499.pdf [firstpage_image] =>[orig_patent_app_number] => 12053481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053481
Circuit type pragma for computer aided design tools Mar 20, 2008 Issued
Array ( [id] => 7972401 [patent_doc_number] => 07941779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Methods and apparatuses for thermal analysis based circuit design' [patent_app_type] => utility [patent_app_number] => 12/053453 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10898 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941779.pdf [firstpage_image] =>[orig_patent_app_number] => 12053453 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053453
Methods and apparatuses for thermal analysis based circuit design Mar 20, 2008 Issued
Array ( [id] => 4455159 [patent_doc_number] => 07966590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Circuit design data conversion apparatus, circuit design data conversion method, and computer product' [patent_app_type] => utility [patent_app_number] => 12/076551 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7769 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966590.pdf [firstpage_image] =>[orig_patent_app_number] => 12076551 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076551
Circuit design data conversion apparatus, circuit design data conversion method, and computer product Mar 18, 2008 Issued
Array ( [id] => 4766926 [patent_doc_number] => 20080178138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same' [patent_app_type] => utility [patent_app_number] => 12/077359 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20080178138.pdf [firstpage_image] =>[orig_patent_app_number] => 12077359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/077359
Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same Mar 17, 2008 Abandoned
Array ( [id] => 4889170 [patent_doc_number] => 20080263502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'MASK PATTERN DATA GENERATING METHOD, INFORMATION PROCESSING APPARATUS, PHOTOMASK FABRICATION SYSTEM, AND IMAGE SENSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/048691 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4598 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263502.pdf [firstpage_image] =>[orig_patent_app_number] => 12048691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048691
Mask pattern data generating method, information processing apparatus, photomask fabrication system, and image sensing apparatus Mar 13, 2008 Issued
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