Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4826350 [patent_doc_number] => 20080229264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Semiconductor evaluation apparatus, semiconductor evaluation method and semiconductor evaluation program' [patent_app_type] => utility [patent_app_number] => 12/071856 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8622 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229264.pdf [firstpage_image] =>[orig_patent_app_number] => 12071856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071856
Semiconductor evaluation apparatus, semiconductor evaluation method and semiconductor evaluation program Feb 26, 2008 Abandoned
Array ( [id] => 7548053 [patent_doc_number] => 08056034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-08 [patent_title] => 'Use of smith chart to compensate for missing data on network performance at lower frequency' [patent_app_type] => utility [patent_app_number] => 12/016151 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6404 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/056/08056034.pdf [firstpage_image] =>[orig_patent_app_number] => 12016151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016151
Use of smith chart to compensate for missing data on network performance at lower frequency Jan 16, 2008 Issued
Array ( [id] => 8120445 [patent_doc_number] => 08161445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Logic transformation and gate placement to avoid routing congestion' [patent_app_type] => utility [patent_app_number] => 12/015631 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4560 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161445.pdf [firstpage_image] =>[orig_patent_app_number] => 12015631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/015631
Logic transformation and gate placement to avoid routing congestion Jan 16, 2008 Issued
Array ( [id] => 8633008 [patent_doc_number] => 08365107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Scanner based optical proximity correction system and method of use' [patent_app_type] => utility [patent_app_number] => 12/521651 [patent_app_country] => US [patent_app_date] => 2008-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10663 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12521651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/521651
Scanner based optical proximity correction system and method of use Jan 15, 2008 Issued
Array ( [id] => 4905680 [patent_doc_number] => 20080115094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'LOGIC TRANSFORMATION AND GATE PLACEMENT TO AVOID ROUTING CONGESTION' [patent_app_type] => utility [patent_app_number] => 12/014344 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4547 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115094.pdf [firstpage_image] =>[orig_patent_app_number] => 12014344 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014344
Logic transformation and gate placement to avoid routing congestion Jan 14, 2008 Issued
Array ( [id] => 4523264 [patent_doc_number] => 07917884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver' [patent_app_type] => utility [patent_app_number] => 12/013191 [patent_app_country] => US [patent_app_date] => 2008-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6850 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917884.pdf [firstpage_image] =>[orig_patent_app_number] => 12013191 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/013191
Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver Jan 10, 2008 Issued
Array ( [id] => 4905679 [patent_doc_number] => 20080115093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'SYSTEMS AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 11/971171 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8039 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115093.pdf [firstpage_image] =>[orig_patent_app_number] => 11971171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971171
Systems and media to improve manufacturability of semiconductor devices Jan 7, 2008 Issued
Array ( [id] => 8985298 [patent_doc_number] => 08516428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Methods, systems, and media to improve manufacturability of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/971179 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 8653 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11971179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/971179
Methods, systems, and media to improve manufacturability of semiconductor devices Jan 7, 2008 Issued
Array ( [id] => 5438042 [patent_doc_number] => 20090172629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Validating continuous signal phase matching in high-speed nets routed as differential pairs' [patent_app_type] => utility [patent_app_number] => 12/006281 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3292 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172629.pdf [firstpage_image] =>[orig_patent_app_number] => 12006281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/006281
Validating continuous signal phase matching in high-speed nets routed as differential pairs Dec 30, 2007 Issued
Array ( [id] => 4869206 [patent_doc_number] => 20080148227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD OF PARTITIONING AN ALGORITHM BETWEEN HARDWARE AND SOFTWARE' [patent_app_type] => utility [patent_app_number] => 11/957287 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4109 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148227.pdf [firstpage_image] =>[orig_patent_app_number] => 11957287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/957287
Method of partitioning an algorithm between hardware and software Dec 13, 2007 Issued
Array ( [id] => 4747489 [patent_doc_number] => 20080092091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Method and system for reduction of XOR/XNOR subexpressions in structural design representations' [patent_app_type] => utility [patent_app_number] => 11/955112 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9882 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092091.pdf [firstpage_image] =>[orig_patent_app_number] => 11955112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955112
Method and system for reduction of XOR/XNOR subexpressions in structural design representations Dec 11, 2007 Issued
Array ( [id] => 4746784 [patent_doc_number] => 20080091386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Method and System for Reduction of XOR/XNOR Subexpressions in Structural Design Representations' [patent_app_type] => utility [patent_app_number] => 11/955152 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9936 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091386.pdf [firstpage_image] =>[orig_patent_app_number] => 11955152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955152
Reduction of XOR/XNOR subexpressions in structural design representations Dec 11, 2007 Issued
Array ( [id] => 4693936 [patent_doc_number] => 20080086707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Method and system for enchanced verification through binary decision diagram-based target decomposition' [patent_app_type] => utility [patent_app_number] => 11/952535 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8621 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086707.pdf [firstpage_image] =>[orig_patent_app_number] => 11952535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952535
Enhanced verification through binary decision diagram-based target decomposition Dec 6, 2007 Issued
Array ( [id] => 4577952 [patent_doc_number] => 07823093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and system for reduction of and/or subexpressions in structural design representations' [patent_app_type] => utility [patent_app_number] => 11/944663 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9928 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823093.pdf [firstpage_image] =>[orig_patent_app_number] => 11944663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944663
Method and system for reduction of and/or subexpressions in structural design representations Nov 25, 2007 Issued
Array ( [id] => 4470395 [patent_doc_number] => 07882459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Method and system for reduction of AND/OR subexpressions in structural design representations' [patent_app_type] => utility [patent_app_number] => 11/944668 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9869 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882459.pdf [firstpage_image] =>[orig_patent_app_number] => 11944668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944668
Method and system for reduction of AND/OR subexpressions in structural design representations Nov 25, 2007 Issued
Array ( [id] => 4784092 [patent_doc_number] => 20080137421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'PATTERN LAYOUT OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/943771 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3751 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20080137421.pdf [firstpage_image] =>[orig_patent_app_number] => 11943771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943771
Pattern layout of integrated circuit Nov 20, 2007 Issued
Array ( [id] => 9116332 [patent_doc_number] => 08572524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Statistical optical proximity correction' [patent_app_type] => utility [patent_app_number] => 11/943591 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3104 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11943591 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943591
Statistical optical proximity correction Nov 20, 2007 Issued
Array ( [id] => 4540956 [patent_doc_number] => 07954079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Method for compensating performance degradation of RFIC using EM simulation' [patent_app_type] => utility [patent_app_number] => 11/943211 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 5597 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/954/07954079.pdf [firstpage_image] =>[orig_patent_app_number] => 11943211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943211
Method for compensating performance degradation of RFIC using EM simulation Nov 19, 2007 Issued
Array ( [id] => 4923879 [patent_doc_number] => 20080072196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Systems, Methods, and Media for Block-Based Assertion Generation, Qualification and Analysis' [patent_app_type] => utility [patent_app_number] => 11/942148 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9155 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072196.pdf [firstpage_image] =>[orig_patent_app_number] => 11942148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942148
Systems, methods, and media for block-based assertion generation, qualification and analysis Nov 18, 2007 Issued
Array ( [id] => 4449101 [patent_doc_number] => 07865853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Systems, methods, and media for block-based assertion generation, qualification and analysis' [patent_app_type] => utility [patent_app_number] => 11/936775 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9183 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865853.pdf [firstpage_image] =>[orig_patent_app_number] => 11936775 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/936775
Systems, methods, and media for block-based assertion generation, qualification and analysis Nov 6, 2007 Issued
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