Jeffrey T. Knapp

Array ( [id] => 4443759 [patent_doc_number] => 07900167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Silicon germanium heterojunction bipolar transistor structure and method' [patent_app_type] => utility [patent_app_number] => 11/923131 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8670 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900167.pdf [firstpage_image] =>[orig_patent_app_number] => 11923131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7718839 [patent_doc_number] => 08095907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Reliability evaluation and system fail warning methods using on chip parametric monitors' [patent_app_type] => utility [patent_app_number] => 11/874950 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2995 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/095/08095907.pdf [firstpage_image] =>[orig_patent_app_number] => 11874950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4917740 [patent_doc_number] => 20080098341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'DESIGN LAYOUT GENERATING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/874601 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098341.pdf [firstpage_image] =>[orig_patent_app_number] => 11874601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500860 [patent_doc_number] => 07904868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Structures including means for lateral current carrying capability improvement in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/873711 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4780 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904868.pdf [firstpage_image] =>[orig_patent_app_number] => 11873711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4499637 [patent_doc_number] => 07886253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Design structure for performing iterative synthesis of an integrated circuit design to attain power closure' [patent_app_type] => utility [patent_app_number] => 11/872731 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886253.pdf [firstpage_image] =>[orig_patent_app_number] => 11872731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4470506 [patent_doc_number] => 07882479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory' [patent_app_type] => utility [patent_app_number] => 11/872191 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3770 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882479.pdf [firstpage_image] =>[orig_patent_app_number] => 11872191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5286710 [patent_doc_number] => 20090100385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'Optimal Simplification of Constraint-Based Testbenches' [patent_app_type] => utility [patent_app_number] => 11/870471 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20090100385.pdf [firstpage_image] =>[orig_patent_app_number] => 11870471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4857886 [patent_doc_number] => 20080266736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Method and Apparatus for Implementing APS Voltage Level Activation With Secondary Chip in Stacked-Chip Technology' [patent_app_type] => utility [patent_app_number] => 11/869841 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2930 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266736.pdf [firstpage_image] =>[orig_patent_app_number] => 11869841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8343241 [patent_doc_number] => 08245179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'RF circuit, circuit evaluation method, algorithm and recording medium' [patent_app_type] => utility [patent_app_number] => 12/312551 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 11908 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 479 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12312551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4945619 [patent_doc_number] => 20080082946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => ' AUTOMATA UNIT, A TOOL FOR DESIGNING CHECKER CIRCUITRY AND A METHOD OF MANUFACTURING HARDWARE CIRCUITRY INCORPORATING CHECKER CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 11/864030 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082946.pdf [firstpage_image] =>[orig_patent_app_number] => 11864030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5510474 [patent_doc_number] => 20090083681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Methods and apparatuses for designing integrated circuits using virtual cells' [patent_app_type] => utility [patent_app_number] => 11/904161 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6514 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083681.pdf [firstpage_image] =>[orig_patent_app_number] => 11904161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4940574 [patent_doc_number] => 20080077894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'METHOD FOR GENERATING A DESIGN RULE MAP HAVING SPATIALLY VARYING OVERLAY BUDGET' [patent_app_type] => utility [patent_app_number] => 11/857301 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6073 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20080077894.pdf [firstpage_image] =>[orig_patent_app_number] => 11857301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7525086 [patent_doc_number] => 08028256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-27 [patent_title] => 'System and method for breaking a feedback loop using a voltage controlled voltage source terminated subnetwork model' [patent_app_type] => utility [patent_app_number] => 11/901521 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028256.pdf [firstpage_image] =>[orig_patent_app_number] => 11901521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4462752 [patent_doc_number] => 07895541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method' [patent_app_type] => utility [patent_app_number] => 11/901030 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4913 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895541.pdf [firstpage_image] =>[orig_patent_app_number] => 11901030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4895266 [patent_doc_number] => 20080104366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Semiconductor chip' [patent_app_type] => utility [patent_app_number] => 11/898241 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4362 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104366.pdf [firstpage_image] =>[orig_patent_app_number] => 11898241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5325574 [patent_doc_number] => 20090063564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Statistical design closure' [patent_app_type] => utility [patent_app_number] => 11/849391 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20090063564.pdf [firstpage_image] =>[orig_patent_app_number] => 11849391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4591304 [patent_doc_number] => 07827514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Efficient electromagnetic modeling of irregular metal planes' [patent_app_type] => utility [patent_app_number] => 11/849346 [patent_app_country] => US [patent_app_date] => 2007-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827514.pdf [firstpage_image] =>[orig_patent_app_number] => 11849346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4735666 [patent_doc_number] => 20080052648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'METHOD AND SYSTEM FOR ENCHANCED VERIFICATION THROUGH BINARY DECISION DIAGRAM-BASED TARGET DECOMPOSITION' [patent_app_type] => utility [patent_app_number] => 11/848356 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052648.pdf [firstpage_image] =>[orig_patent_app_number] => 11848356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8645782 [patent_doc_number] => 08370781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Computer product for supporting design and verification of integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/896301 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9773 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11896301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4733697 [patent_doc_number] => 20080050676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD, DATA GENERATING APPARATUS, DATA GENERATING METHOD AND RECORDING MEDIUM READABLE BY COMPUTER RECODED WITH DATA GENERATING PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/844541 [patent_app_country] => US [patent_app_date] => 2007-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20080050676.pdf [firstpage_image] =>[orig_patent_app_number] => 11844541 [rel_patent_id] =>[rel_patent_doc_number] =>)