
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19194
[patent_doc_number] => 07810065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'System and method for implementing optimized creation of openings for de-gassing in an electronic package'
[patent_app_type] => utility
[patent_app_number] => 11/844861
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2292
[patent_no_of_claims] => 12
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[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/810/07810065.pdf
[firstpage_image] =>[orig_patent_app_number] => 11844861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844861 | System and method for implementing optimized creation of openings for de-gassing in an electronic package | Aug 23, 2007 | Issued |
Array
(
[id] => 5232545
[patent_doc_number] => 20070294654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'METHOD FOR USING MIXED MULTI-VT DEVICES IN A CELL-BASED DESIGN'
[patent_app_type] => utility
[patent_app_number] => 11/844698
[patent_app_country] => US
[patent_app_date] => 2007-08-24
[patent_effective_date] => 0000-00-00
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[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0294/20070294654.pdf
[firstpage_image] =>[orig_patent_app_number] => 11844698
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/844698 | Method for using mixed multi-Vt devices in a cell-based design | Aug 23, 2007 | Issued |
Array
(
[id] => 7768463
[patent_doc_number] => 08117580
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-14
[patent_title] => 'Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein'
[patent_app_type] => utility
[patent_app_number] => 11/895132
[patent_app_country] => US
[patent_app_date] => 2007-08-23
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 9934
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[pdf_file] => patents/08/117/08117580.pdf
[firstpage_image] =>[orig_patent_app_number] => 11895132
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/895132 | Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein | Aug 22, 2007 | Issued |
Array
(
[id] => 4905687
[patent_doc_number] => 20080115101
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Program conversion apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/889571
[patent_app_country] => US
[patent_app_date] => 2007-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[firstpage_image] =>[orig_patent_app_number] => 11889571
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/889571 | Program conversion apparatus | Aug 13, 2007 | Abandoned |
Array
(
[id] => 7972397
[patent_doc_number] => 07941777
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-10
[patent_title] => 'Generating a module interface for partial reconfiguration design flows'
[patent_app_type] => utility
[patent_app_number] => 11/891141
[patent_app_country] => US
[patent_app_date] => 2007-08-08
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[pdf_file] => patents/07/941/07941777.pdf
[firstpage_image] =>[orig_patent_app_number] => 11891141
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/891141 | Generating a module interface for partial reconfiguration design flows | Aug 7, 2007 | Issued |
Array
(
[id] => 4735665
[patent_doc_number] => 20080052647
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[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'COMPUTER DEVELOPMENT APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/835521
[patent_app_country] => US
[patent_app_date] => 2007-08-08
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[firstpage_image] =>[orig_patent_app_number] => 11835521
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/835521 | COMPUTER DEVELOPMENT APPARATUS | Aug 7, 2007 | Abandoned |
Array
(
[id] => 5418272
[patent_doc_number] => 20090044159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'False path handling'
[patent_app_type] => utility
[patent_app_number] => 11/890951
[patent_app_country] => US
[patent_app_date] => 2007-08-08
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[pdf_file] => publications/A1/0044/20090044159.pdf
[firstpage_image] =>[orig_patent_app_number] => 11890951
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/890951 | False path handling | Aug 7, 2007 | Abandoned |
Array
(
[id] => 5523283
[patent_doc_number] => 20090031264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-29
[patent_title] => 'System and method for finding electromigration, self heat and voltage drop violations of an integrated circuit when its design and electrical characterization are incomplete'
[patent_app_type] => utility
[patent_app_number] => 11/880611
[patent_app_country] => US
[patent_app_date] => 2007-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0031/20090031264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11880611
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/880611 | System and method for finding electromigration, self heat and voltage drop violations of an integrated circuit when its design and electrical characterization are incomplete | Jul 23, 2007 | Abandoned |
Array
(
[id] => 47987
[patent_doc_number] => 07784016
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-24
[patent_title] => 'Method and system for context-specific mask writing'
[patent_app_type] => utility
[patent_app_number] => 11/781801
[patent_app_country] => US
[patent_app_date] => 2007-07-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/784/07784016.pdf
[firstpage_image] =>[orig_patent_app_number] => 11781801
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/781801 | Method and system for context-specific mask writing | Jul 22, 2007 | Issued |
Array
(
[id] => 4804896
[patent_doc_number] => 20080016485
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'Mothod and system for designing a timing closure of an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/826723
[patent_app_country] => US
[patent_app_date] => 2007-07-18
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[pdf_file] => publications/A1/0016/20080016485.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826723 | Method and system for designing a timing closure of an integrated circuit | Jul 17, 2007 | Issued |
Array
(
[id] => 4802922
[patent_doc_number] => 20080014510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'PHOTOMASK DESIGNING APPARATUS, PHOTOMASK, PHOTOMASK DESIGNING METHOD, PHOTOMASK DESIGNING PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM ON WHICH THE PHOTOMASK DESIGNING PROGRAM IS STORED'
[patent_app_type] => utility
[patent_app_number] => 11/777481
[patent_app_country] => US
[patent_app_date] => 2007-07-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0014/20080014510.pdf
[firstpage_image] =>[orig_patent_app_number] => 11777481
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777481 | PHOTOMASK DESIGNING APPARATUS, PHOTOMASK, PHOTOMASK DESIGNING METHOD, PHOTOMASK DESIGNING PROGRAM AND COMPUTER-READABLE STORAGE MEDIUM ON WHICH THE PHOTOMASK DESIGNING PROGRAM IS STORED | Jul 12, 2007 | Abandoned |
Array
(
[id] => 118494
[patent_doc_number] => 07716625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Logic circuit and method of logic circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/826281
[patent_app_country] => US
[patent_app_date] => 2007-07-13
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[pdf_file] => patents/07/716/07716625.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826281
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826281 | Logic circuit and method of logic circuit design | Jul 12, 2007 | Issued |
Array
(
[id] => 5312128
[patent_doc_number] => 20090019409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-15
[patent_title] => 'Method for Reducing Timing Libraries for Intra-Die Model in Statistical Static Timing Analysis'
[patent_app_type] => utility
[patent_app_number] => 11/777761
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777761 | Method for reducing timing libraries for intra-die model in statistical static timing analysis | Jul 12, 2007 | Issued |
Array
(
[id] => 4592938
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[patent_issue_date] => 2010-12-14
[patent_title] => 'Fanout-optimization during physical synthesis for placed circuit designs'
[patent_app_type] => utility
[patent_app_number] => 11/827531
[patent_app_country] => US
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Array
(
[id] => 4443760
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[patent_kind] => B2
[patent_issue_date] => 2011-03-01
[patent_title] => 'Customizable synthesis of tunable parameters for code generation'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/776891 | Customizable synthesis of tunable parameters for code generation | Jul 11, 2007 | Issued |
Array
(
[id] => 4621781
[patent_doc_number] => 08001512
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-08-16
[patent_title] => 'Method and system for implementing context simulation'
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Array
(
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[patent_issue_date] => 2008-12-25
[patent_title] => 'EFFICIENT CELL SWAPPING SYSTEM FOR LEAKAGE POWER REDUCTION IN A MULTI-THRESHOLD VOLTAGE PROCESS'
[patent_app_type] => utility
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Array
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[patent_title] => 'System and method to improve chip yield, reliability and performance'
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Array
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Array
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[patent_issue_date] => 2011-01-04
[patent_title] => 'Method, system, and article of manufacture for implementing metal-fill with power or ground connection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/760711 | Method, system, and article of manufacture for implementing metal-fill with power or ground connection | Jun 7, 2007 | Issued |