Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4951256 [patent_doc_number] => 20080307382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS' [patent_app_type] => utility [patent_app_number] => 11/758571 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6711 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307382.pdf [firstpage_image] =>[orig_patent_app_number] => 11758571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758571
Combination of ground devices in wiring harness designs Jun 4, 2007 Issued
Array ( [id] => 4919115 [patent_doc_number] => 20080067426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'PATTERN WRITING CIRCUIT SELF-DIAGNOSIS METHOD FOR CHARGED BEAM PHOTOLITHOGRAPHY APPARATUS AND CHARGED BEAM PHOTOLITHOGRAPHY APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/754771 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20080067426.pdf [firstpage_image] =>[orig_patent_app_number] => 11754771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754771
Pattern writing circuit self-diagnosis method for charged beam photolithography apparatus and charged beam photolithography apparatus May 28, 2007 Issued
Array ( [id] => 5087092 [patent_doc_number] => 20070277143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Skeleton generation apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/805141 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6687 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277143.pdf [firstpage_image] =>[orig_patent_app_number] => 11805141 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805141
Skeleton generation apparatus and method May 21, 2007 Issued
Array ( [id] => 146843 [patent_doc_number] => 07689941 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Write margin calculation tool for dual-port random-access-memory circuitry' [patent_app_type] => utility [patent_app_number] => 11/803091 [patent_app_country] => US [patent_app_date] => 2007-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689941.pdf [firstpage_image] =>[orig_patent_app_number] => 11803091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/803091
Write margin calculation tool for dual-port random-access-memory circuitry May 10, 2007 Issued
Array ( [id] => 4508938 [patent_doc_number] => 07958470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method and system for false path analysis' [patent_app_type] => utility [patent_app_number] => 11/745381 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5567 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958470.pdf [firstpage_image] =>[orig_patent_app_number] => 11745381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/745381
Method and system for false path analysis May 6, 2007 Issued
Array ( [id] => 97623 [patent_doc_number] => 07739645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Method and apparatus for determining a process model using a 2-D-pattern detecting kernel' [patent_app_type] => utility [patent_app_number] => 11/800171 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739645.pdf [firstpage_image] =>[orig_patent_app_number] => 11800171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/800171
Method and apparatus for determining a process model using a 2-D-pattern detecting kernel May 3, 2007 Issued
Array ( [id] => 158029 [patent_doc_number] => 07685540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Standard block design: an effective approach for large scale floorplanning' [patent_app_type] => utility [patent_app_number] => 11/744208 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685540.pdf [firstpage_image] =>[orig_patent_app_number] => 11744208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/744208
Standard block design: an effective approach for large scale floorplanning May 2, 2007 Issued
Array ( [id] => 97615 [patent_doc_number] => 07739642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Optimizing integrated circuit design through balanced combinational slack plus sequential slack' [patent_app_type] => utility [patent_app_number] => 11/743279 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 49 [patent_no_of_words] => 26127 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739642.pdf [firstpage_image] =>[orig_patent_app_number] => 11743279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/743279
Optimizing integrated circuit design through balanced combinational slack plus sequential slack May 1, 2007 Issued
Array ( [id] => 87957 [patent_doc_number] => 07743354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Optimizing integrated circuit design through use of sequential timing information' [patent_app_type] => utility [patent_app_number] => 11/743301 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 49 [patent_no_of_words] => 27417 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743354.pdf [firstpage_image] =>[orig_patent_app_number] => 11743301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/743301
Optimizing integrated circuit design through use of sequential timing information May 1, 2007 Issued
Array ( [id] => 4961789 [patent_doc_number] => 20080276214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/742970 [patent_app_country] => US [patent_app_date] => 2007-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2426 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276214.pdf [firstpage_image] =>[orig_patent_app_number] => 11742970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742970
METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE Apr 30, 2007 Abandoned
Array ( [id] => 97601 [patent_doc_number] => 07739634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Verification equipment of semiconductor integrated circuit, method of verifying semiconductor integrated circuit and process of manufacture of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/742287 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 11025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739634.pdf [firstpage_image] =>[orig_patent_app_number] => 11742287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742287
Verification equipment of semiconductor integrated circuit, method of verifying semiconductor integrated circuit and process of manufacture of semiconductor device Apr 29, 2007 Issued
Array ( [id] => 4862662 [patent_doc_number] => 20080270969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHOD FOR CORRECTING PHOTOMASK PATTERN' [patent_app_type] => utility [patent_app_number] => 11/742372 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3480 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270969.pdf [firstpage_image] =>[orig_patent_app_number] => 11742372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/742372
Method for correcting photomask pattern Apr 29, 2007 Issued
Array ( [id] => 4861250 [patent_doc_number] => 20080270100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Method, Apparatus, and Computer Program Product for Implementing Optimized Channel Routing With Generation of FIR Coefficients' [patent_app_type] => utility [patent_app_number] => 11/741261 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270100.pdf [firstpage_image] =>[orig_patent_app_number] => 11741261 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741261
Method, Apparatus, and Computer Program Product for Implementing Optimized Channel Routing With Generation of FIR Coefficients Apr 26, 2007 Abandoned
Array ( [id] => 4857396 [patent_doc_number] => 20080266246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'TRAVERSING GRAPHICAL LAYERS USING A SCROLLING MECHANISM IN A PHYSICAL DESIGN ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/739911 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2438 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20080266246.pdf [firstpage_image] =>[orig_patent_app_number] => 11739911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739911
TRAVERSING GRAPHICAL LAYERS USING A SCROLLING MECHANISM IN A PHYSICAL DESIGN ENVIRONMENT Apr 24, 2007 Abandoned
Array ( [id] => 4862656 [patent_doc_number] => 20080270965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/739251 [patent_app_country] => US [patent_app_date] => 2007-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270965.pdf [firstpage_image] =>[orig_patent_app_number] => 11739251 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739251
METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM Apr 23, 2007 Abandoned
Array ( [id] => 336965 [patent_doc_number] => 07509598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Clock boosting systems and methods' [patent_app_type] => utility [patent_app_number] => 11/737702 [patent_app_country] => US [patent_app_date] => 2007-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4792 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509598.pdf [firstpage_image] =>[orig_patent_app_number] => 11737702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/737702
Clock boosting systems and methods Apr 18, 2007 Issued
Array ( [id] => 4684145 [patent_doc_number] => 20080250371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Delay Budget Allocation with Path Trimming' [patent_app_type] => utility [patent_app_number] => 11/733091 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10919 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250371.pdf [firstpage_image] =>[orig_patent_app_number] => 11733091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733091
Delay budget allocation with path trimming Apr 8, 2007 Issued
Array ( [id] => 171996 [patent_doc_number] => 07669164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-23 [patent_title] => 'Hardware and software implementation of an electronic design in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/732611 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669164.pdf [firstpage_image] =>[orig_patent_app_number] => 11732611 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732611
Hardware and software implementation of an electronic design in a programmable logic device Apr 3, 2007 Issued
Array ( [id] => 116846 [patent_doc_number] => 07721244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'LSI circuit designing system, antenna damage preventing method and prevention controlling program used in same' [patent_app_type] => utility [patent_app_number] => 11/730211 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 10033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721244.pdf [firstpage_image] =>[orig_patent_app_number] => 11730211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/730211
LSI circuit designing system, antenna damage preventing method and prevention controlling program used in same Mar 29, 2007 Issued
Array ( [id] => 188782 [patent_doc_number] => 07647571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method of identifying state nodes at the transistor level in a sequential digital circuit' [patent_app_type] => utility [patent_app_number] => 11/729153 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647571.pdf [firstpage_image] =>[orig_patent_app_number] => 11729153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729153
Method of identifying state nodes at the transistor level in a sequential digital circuit Mar 27, 2007 Issued
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