
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4951256
[patent_doc_number] => 20080307382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-11
[patent_title] => 'COMBINATION OF GROUND DEVICES IN WIRING HARNESS DESIGNS'
[patent_app_type] => utility
[patent_app_number] => 11/758571
[patent_app_country] => US
[patent_app_date] => 2007-06-05
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[pdf_file] => publications/A1/0307/20080307382.pdf
[firstpage_image] =>[orig_patent_app_number] => 11758571
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/758571 | Combination of ground devices in wiring harness designs | Jun 4, 2007 | Issued |
Array
(
[id] => 4919115
[patent_doc_number] => 20080067426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'PATTERN WRITING CIRCUIT SELF-DIAGNOSIS METHOD FOR CHARGED BEAM PHOTOLITHOGRAPHY APPARATUS AND CHARGED BEAM PHOTOLITHOGRAPHY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/754771
[patent_app_country] => US
[patent_app_date] => 2007-05-29
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[firstpage_image] =>[orig_patent_app_number] => 11754771
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754771 | Pattern writing circuit self-diagnosis method for charged beam photolithography apparatus and charged beam photolithography apparatus | May 28, 2007 | Issued |
Array
(
[id] => 5087092
[patent_doc_number] => 20070277143
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[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'Skeleton generation apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 11/805141
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[patent_app_date] => 2007-05-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/805141 | Skeleton generation apparatus and method | May 21, 2007 | Issued |
Array
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[patent_doc_number] => 07689941
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[patent_kind] => B1
[patent_issue_date] => 2010-03-30
[patent_title] => 'Write margin calculation tool for dual-port random-access-memory circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/803091
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/803091 | Write margin calculation tool for dual-port random-access-memory circuitry | May 10, 2007 | Issued |
Array
(
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[patent_title] => 'Method and system for false path analysis'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745381 | Method and system for false path analysis | May 6, 2007 | Issued |
Array
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[patent_title] => 'Method and apparatus for determining a process model using a 2-D-pattern detecting kernel'
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Array
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[patent_title] => 'Standard block design: an effective approach for large scale floorplanning'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744208 | Standard block design: an effective approach for large scale floorplanning | May 2, 2007 | Issued |
Array
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[patent_issue_date] => 2010-06-15
[patent_title] => 'Optimizing integrated circuit design through balanced combinational slack plus sequential slack'
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[patent_app_number] => 11/743279
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743279 | Optimizing integrated circuit design through balanced combinational slack plus sequential slack | May 1, 2007 | Issued |
Array
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[id] => 87957
[patent_doc_number] => 07743354
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[patent_title] => 'Optimizing integrated circuit design through use of sequential timing information'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743301 | Optimizing integrated circuit design through use of sequential timing information | May 1, 2007 | Issued |
Array
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[patent_issue_date] => 2008-11-06
[patent_title] => 'METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 11/742970
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742970 | METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE | Apr 30, 2007 | Abandoned |
Array
(
[id] => 97601
[patent_doc_number] => 07739634
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[patent_title] => 'Verification equipment of semiconductor integrated circuit, method of verifying semiconductor integrated circuit and process of manufacture of semiconductor device'
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Array
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[patent_title] => 'METHOD FOR CORRECTING PHOTOMASK PATTERN'
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Array
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Array
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