Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10717015 [patent_doc_number] => 20160063162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW' [patent_app_type] => utility [patent_app_number] => 14/812109 [patent_app_country] => US [patent_app_date] => 2015-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2773 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14812109 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/812109
SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW Jul 28, 2015 Abandoned
Array ( [id] => 11724468 [patent_doc_number] => 09697323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Accelerated and accuracy-enhanced delay and noise injection calculation for analysis of a digital circuit using grid computing' [patent_app_type] => utility [patent_app_number] => 14/811663 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14070 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14811663 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/811663
Accelerated and accuracy-enhanced delay and noise injection calculation for analysis of a digital circuit using grid computing Jul 27, 2015 Issued
Array ( [id] => 11817098 [patent_doc_number] => 09721051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Reducing clock skew in synthesized modules' [patent_app_type] => utility [patent_app_number] => 14/810887 [patent_app_country] => US [patent_app_date] => 2015-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14810887 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/810887
Reducing clock skew in synthesized modules Jul 27, 2015 Issued
Array ( [id] => 11890110 [patent_doc_number] => 09760672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling' [patent_app_type] => utility [patent_app_number] => 14/791430 [patent_app_country] => US [patent_app_date] => 2015-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7805 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791430
Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling Jul 3, 2015 Issued
Array ( [id] => 11062917 [patent_doc_number] => 20160259879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'SYSTEM AND METHOD FOR NETLIST CLOCK DOMAIN CROSSING VERIFICATION' [patent_app_type] => utility [patent_app_number] => 14/790318 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4186 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14790318 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/790318
System and method for netlist clock domain crossing verification Jul 1, 2015 Issued
Array ( [id] => 11644294 [patent_doc_number] => 09665673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Input capacitance modeling for circuit performance' [patent_app_type] => utility [patent_app_number] => 14/790790 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8218 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14790790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/790790
Input capacitance modeling for circuit performance Jul 1, 2015 Issued
Array ( [id] => 11903652 [patent_doc_number] => 09773086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs' [patent_app_type] => utility [patent_app_number] => 14/791132 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13027 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791132
Methods, systems, and articles of manufacture for implementing coplanar waveguide transmission lines in electronic designs Jul 1, 2015 Issued
Array ( [id] => 10417126 [patent_doc_number] => 20150302136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells Using Filters' [patent_app_type] => utility [patent_app_number] => 14/733332 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733332 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733332
Methods for layout verification for polysilicon cell edge structures in FinFET standard cells using filters Jun 7, 2015 Issued
Array ( [id] => 10486930 [patent_doc_number] => 20150371950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DEVICE DESIGN APPARATUS, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/732491 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 11360 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732491
Semiconductor device, semiconductor device design method, semiconductor device design apparatus, and program Jun 4, 2015 Issued
Array ( [id] => 12257423 [patent_doc_number] => 09929579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method and apparatus for controlling charging of low voltage battery' [patent_app_type] => utility [patent_app_number] => 14/709561 [patent_app_country] => US [patent_app_date] => 2015-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5336 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/709561
Method and apparatus for controlling charging of low voltage battery May 11, 2015 Issued
Array ( [id] => 11810995 [patent_doc_number] => 09715566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Computer implemented system and method of translation of verification commands of an electronic design' [patent_app_type] => utility [patent_app_number] => 14/707689 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11586 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707689 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707689
Computer implemented system and method of translation of verification commands of an electronic design May 7, 2015 Issued
Array ( [id] => 11598958 [patent_doc_number] => 09646128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'System and method for validating stacked dies by comparing connections' [patent_app_type] => utility [patent_app_number] => 14/705021 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705021
System and method for validating stacked dies by comparing connections May 5, 2015 Issued
Array ( [id] => 11431253 [patent_doc_number] => 09569572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Selectively loading design data for logical equivalency check' [patent_app_type] => utility [patent_app_number] => 14/705699 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705699
Selectively loading design data for logical equivalency check May 5, 2015 Issued
Array ( [id] => 10732004 [patent_doc_number] => 20160078154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'DIGITAL CIRCUIT DESIGN METHOD AND ASSOCIATED COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/703905 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2330 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703905 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/703905
Digital circuit design method and associated computer program product May 4, 2015 Issued
Array ( [id] => 11345544 [patent_doc_number] => 09529952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'Speculative circuit design component graphical user interface' [patent_app_type] => utility [patent_app_number] => 14/704721 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 12042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/704721
Speculative circuit design component graphical user interface May 4, 2015 Issued
Array ( [id] => 11124416 [patent_doc_number] => 20160321390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'IMPLEMENTING INTEGRATED CIRCUIT DESIGNS USING DEPOPULATION AND REPOPULATION OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/702627 [patent_app_country] => US [patent_app_date] => 2015-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10584 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/702627
Implementing integrated circuit designs using depopulation and repopulation operations Apr 30, 2015 Issued
Array ( [id] => 11095363 [patent_doc_number] => 20160292332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SYSTEM FOR VERIFYING TIMING CONSTRAINTS OF IC DESIGN' [patent_app_type] => utility [patent_app_number] => 14/675752 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675752 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675752
System for verifying timing constraints of IC design Mar 31, 2015 Issued
Array ( [id] => 11095364 [patent_doc_number] => 20160292333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'CONFIGURABLE DELAY CELL' [patent_app_type] => utility [patent_app_number] => 14/675757 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675757 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675757
Configurable delay cell Mar 31, 2015 Issued
Array ( [id] => 11680564 [patent_doc_number] => 09679096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Method for retrieving a wiring schematic of an electrical installation' [patent_app_type] => utility [patent_app_number] => 14/676072 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676072
Method for retrieving a wiring schematic of an electrical installation Mar 31, 2015 Issued
Array ( [id] => 11614722 [patent_doc_number] => 09652579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-16 [patent_title] => 'Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs' [patent_app_type] => utility [patent_app_number] => 14/675426 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 15398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675426
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs Mar 30, 2015 Issued
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