Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7972381 [patent_doc_number] => 07941769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method and apparatus for integrated circuits design security' [patent_app_type] => utility [patent_app_number] => 11/729371 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2814 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941769.pdf [firstpage_image] =>[orig_patent_app_number] => 11729371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729371
Method and apparatus for integrated circuits design security Mar 27, 2007 Issued
Array ( [id] => 97578 [patent_doc_number] => 07739630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Optimizing a circuit design' [patent_app_type] => utility [patent_app_number] => 11/725191 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 7049 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739630.pdf [firstpage_image] =>[orig_patent_app_number] => 11725191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725191
Optimizing a circuit design Mar 14, 2007 Issued
Array ( [id] => 166939 [patent_doc_number] => 07673270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method and apparatus for compensating an integrated circuit layout for mechanical stress effects' [patent_app_type] => utility [patent_app_number] => 11/717811 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3897 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673270.pdf [firstpage_image] =>[orig_patent_app_number] => 11717811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717811
Method and apparatus for compensating an integrated circuit layout for mechanical stress effects Mar 12, 2007 Issued
Array ( [id] => 58376 [patent_doc_number] => 07774735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-10 [patent_title] => 'Integrated circuit netlist migration' [patent_app_type] => utility [patent_app_number] => 11/683401 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5461 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774735.pdf [firstpage_image] =>[orig_patent_app_number] => 11683401 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683401
Integrated circuit netlist migration Mar 6, 2007 Issued
Array ( [id] => 5260811 [patent_doc_number] => 20070214444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/683121 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6117 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214444.pdf [firstpage_image] =>[orig_patent_app_number] => 11683121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683121
Semiconductor memory device and semiconductor device Mar 6, 2007 Issued
Array ( [id] => 158074 [patent_doc_number] => 07685558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Method for detection and scoring of hot spots in a design layout' [patent_app_type] => utility [patent_app_number] => 11/682640 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685558.pdf [firstpage_image] =>[orig_patent_app_number] => 11682640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682640
Method for detection and scoring of hot spots in a design layout Mar 5, 2007 Issued
Array ( [id] => 4700395 [patent_doc_number] => 20080222579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Moment-Based Method and System for Evaluation of Metal Layer Transient Currents in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/682450 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3433 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222579.pdf [firstpage_image] =>[orig_patent_app_number] => 11682450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682450
Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit Mar 5, 2007 Issued
Array ( [id] => 1078950 [patent_doc_number] => 07617471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Processor event interface for programmable integrated circuit based circuit designs' [patent_app_type] => utility [patent_app_number] => 11/714041 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5676 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/617/07617471.pdf [firstpage_image] =>[orig_patent_app_number] => 11714041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714041
Processor event interface for programmable integrated circuit based circuit designs Mar 4, 2007 Issued
Array ( [id] => 4730912 [patent_doc_number] => 20080209376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP' [patent_app_type] => utility [patent_app_number] => 11/680110 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209376.pdf [firstpage_image] =>[orig_patent_app_number] => 11680110 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680110
System and method for sign-off timing closure of a VLSI chip Feb 27, 2007 Issued
Array ( [id] => 4730908 [patent_doc_number] => 20080209373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 11/679251 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5431 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209373.pdf [firstpage_image] =>[orig_patent_app_number] => 11679251 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679251
Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis Feb 26, 2007 Issued
Array ( [id] => 163557 [patent_doc_number] => 07676769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Adaptive threshold wafer testing device and method thereof' [patent_app_type] => utility [patent_app_number] => 11/678971 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4876 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676769.pdf [firstpage_image] =>[orig_patent_app_number] => 11678971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678971
Adaptive threshold wafer testing device and method thereof Feb 25, 2007 Issued
Array ( [id] => 4874950 [patent_doc_number] => 20080201684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'SIMULATION SITE PLACEMENT FOR LITHOGRAPHIC PROCESS MODELS' [patent_app_type] => utility [patent_app_number] => 11/615221 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4013 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201684.pdf [firstpage_image] =>[orig_patent_app_number] => 11615221 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615221
Simulation site placement for lithographic process models Feb 19, 2007 Issued
Array ( [id] => 258244 [patent_doc_number] => 07577932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Gate modeling for semiconductor fabrication process effects' [patent_app_type] => utility [patent_app_number] => 11/707661 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4960 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577932.pdf [firstpage_image] =>[orig_patent_app_number] => 11707661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707661
Gate modeling for semiconductor fabrication process effects Feb 15, 2007 Issued
Array ( [id] => 4874383 [patent_doc_number] => 20080201117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'DYNAMIC SAMPLING WITH EFFICIENT MODEL FOR OVERLAY' [patent_app_type] => utility [patent_app_number] => 11/676258 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201117.pdf [firstpage_image] =>[orig_patent_app_number] => 11676258 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/676258
Dynamic sampling with efficient model for overlay Feb 15, 2007 Issued
Array ( [id] => 172002 [patent_doc_number] => 07669170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Circuit layout methodology using via shape process' [patent_app_type] => utility [patent_app_number] => 11/676185 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4641 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669170.pdf [firstpage_image] =>[orig_patent_app_number] => 11676185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/676185
Circuit layout methodology using via shape process Feb 15, 2007 Issued
Array ( [id] => 5167288 [patent_doc_number] => 20070288877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Design support method, design support apparatus, computer product' [patent_app_type] => utility [patent_app_number] => 11/706211 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6503 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288877.pdf [firstpage_image] =>[orig_patent_app_number] => 11706211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706211
Design support method, design support apparatus, computer product Feb 14, 2007 Issued
Array ( [id] => 97626 [patent_doc_number] => 07739648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Formation of masks/reticles having dummy features' [patent_app_type] => utility [patent_app_number] => 11/673611 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3907 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739648.pdf [firstpage_image] =>[orig_patent_app_number] => 11673611 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673611
Formation of masks/reticles having dummy features Feb 11, 2007 Issued
Array ( [id] => 5255257 [patent_doc_number] => 20070136713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Method and Apparatus for Routing' [patent_app_type] => utility [patent_app_number] => 11/673429 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12000 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136713.pdf [firstpage_image] =>[orig_patent_app_number] => 11673429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673429
Method and apparatus for routing Feb 8, 2007 Issued
Array ( [id] => 4990797 [patent_doc_number] => 20070157138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Management of functions for block diagrams' [patent_app_type] => utility [patent_app_number] => 11/703336 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 22383 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157138.pdf [firstpage_image] =>[orig_patent_app_number] => 11703336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703336
Management of functions for block diagrams Feb 5, 2007 Issued
Array ( [id] => 5233911 [patent_doc_number] => 20070126066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'SEMICONDUCTOR CELL WITH POWER LAYOUT NOT CONTACTING SIDES OF ITS RECTANGULAR BOUNDARY AND SEMICONDUCTOR CIRCUIT UTILIZING SEMICONDUCTOR CELLS' [patent_app_type] => utility [patent_app_number] => 11/670430 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2658 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126066.pdf [firstpage_image] =>[orig_patent_app_number] => 11670430 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670430
Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells Feb 1, 2007 Issued
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