Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 28587 [patent_doc_number] => 07797659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Analog/digital partitioning of circuit designs for simulation' [patent_app_type] => utility [patent_app_number] => 11/699881 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6975 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797659.pdf [firstpage_image] =>[orig_patent_app_number] => 11699881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699881
Analog/digital partitioning of circuit designs for simulation Jan 28, 2007 Issued
Array ( [id] => 7972383 [patent_doc_number] => 07941770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'System and method for implementing an online design platform for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/626951 [patent_app_country] => US [patent_app_date] => 2007-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941770.pdf [firstpage_image] =>[orig_patent_app_number] => 11626951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626951
System and method for implementing an online design platform for integrated circuits Jan 24, 2007 Issued
Array ( [id] => 4766756 [patent_doc_number] => 20080177968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'RANDOM STIMULI GENERATION OF MEMORY MAPS AND MEMORY ALLOCATIONS' [patent_app_type] => utility [patent_app_number] => 11/625831 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20080177968.pdf [firstpage_image] =>[orig_patent_app_number] => 11625831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625831
Random stimuli generation of memory maps and memory allocations Jan 22, 2007 Issued
Array ( [id] => 28566 [patent_doc_number] => 07797649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-14 [patent_title] => 'Method and system for implementing an analytical wirelength formulation' [patent_app_type] => utility [patent_app_number] => 11/656791 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5451 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797649.pdf [firstpage_image] =>[orig_patent_app_number] => 11656791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/656791
Method and system for implementing an analytical wirelength formulation Jan 21, 2007 Issued
Array ( [id] => 4925545 [patent_doc_number] => 20080164908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Data-Driven Finite State Machine Engine for Flow Control' [patent_app_type] => utility [patent_app_number] => 11/619691 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8170 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20080164908.pdf [firstpage_image] =>[orig_patent_app_number] => 11619691 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619691
Data-driven finite state machine engine for flow control Jan 3, 2007 Issued
Array ( [id] => 599155 [patent_doc_number] => 07448009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Method of leakage optimization in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/619341 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/448/07448009.pdf [firstpage_image] =>[orig_patent_app_number] => 11619341 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619341
Method of leakage optimization in integrated circuit design Jan 2, 2007 Issued
Array ( [id] => 245211 [patent_doc_number] => 07590955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method and system for implementing layout, placement, and routing with merged shapes' [patent_app_type] => utility [patent_app_number] => 11/648151 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3856 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590955.pdf [firstpage_image] =>[orig_patent_app_number] => 11648151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648151
Method and system for implementing layout, placement, and routing with merged shapes Dec 28, 2006 Issued
Array ( [id] => 5190586 [patent_doc_number] => 20070168895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/646321 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10249 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168895.pdf [firstpage_image] =>[orig_patent_app_number] => 11646321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646321
Automatic design method of semiconductor integrated circuit, automatic design system of semiconductor integrated circuit, and semiconductor integrated circuit Dec 27, 2006 Issued
Array ( [id] => 4882100 [patent_doc_number] => 20080155483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Database-aided circuit design system and method therefor' [patent_app_type] => utility [patent_app_number] => 11/643891 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3192 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155483.pdf [firstpage_image] =>[orig_patent_app_number] => 11643891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643891
Database-aided circuit design system and method therefor Dec 21, 2006 Issued
Array ( [id] => 4799037 [patent_doc_number] => 20080010623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Semiconductor device verification system and semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 11/640231 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010623.pdf [firstpage_image] =>[orig_patent_app_number] => 11640231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640231
Semiconductor device verification system and semiconductor device fabrication method Dec 17, 2006 Issued
Array ( [id] => 188795 [patent_doc_number] => 07647576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Net/wiring selection method, net selection method, wiring selection method, and delay improvement method' [patent_app_type] => utility [patent_app_number] => 11/637731 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 10052 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647576.pdf [firstpage_image] =>[orig_patent_app_number] => 11637731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637731
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method Dec 12, 2006 Issued
Array ( [id] => 9124 [patent_doc_number] => 07818707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Fast pattern matching' [patent_app_type] => utility [patent_app_number] => 11/609901 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7673 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818707.pdf [firstpage_image] =>[orig_patent_app_number] => 11609901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609901
Fast pattern matching Dec 11, 2006 Issued
Array ( [id] => 220663 [patent_doc_number] => 07614022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-03 [patent_title] => 'Testing for bridge faults in the interconnect of programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/633921 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/614/07614022.pdf [firstpage_image] =>[orig_patent_app_number] => 11633921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633921
Testing for bridge faults in the interconnect of programmable integrated circuits Dec 4, 2006 Issued
Array ( [id] => 4833241 [patent_doc_number] => 20080131788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD TO AUTOMATICALLY REPAIR TRIM PHOTOMASK DESIGN RULE VIOLATIONS FOR ALTERNATING PHASE SHIFT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 11/565161 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2780 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20080131788.pdf [firstpage_image] =>[orig_patent_app_number] => 11565161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565161
METHOD TO AUTOMATICALLY REPAIR TRIM PHOTOMASK DESIGN RULE VIOLATIONS FOR ALTERNATING PHASE SHIFT LITHOGRAPHY Nov 29, 2006 Abandoned
Array ( [id] => 5260812 [patent_doc_number] => 20070214445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Element placement method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/606811 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214445.pdf [firstpage_image] =>[orig_patent_app_number] => 11606811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/606811
Element placement method and apparatus Nov 28, 2006 Abandoned
Array ( [id] => 27582 [patent_doc_number] => 07802213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method and apparatus for circuit design and retiming' [patent_app_type] => utility [patent_app_number] => 11/605554 [patent_app_country] => US [patent_app_date] => 2006-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10974 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802213.pdf [firstpage_image] =>[orig_patent_app_number] => 11605554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605554
Method and apparatus for circuit design and retiming Nov 26, 2006 Issued
Array ( [id] => 272398 [patent_doc_number] => 07565638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Density-based layer filler for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/562301 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 14072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/565/07565638.pdf [firstpage_image] =>[orig_patent_app_number] => 11562301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/562301
Density-based layer filler for integrated circuit design Nov 20, 2006 Issued
Array ( [id] => 241485 [patent_doc_number] => 07594211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Methods and apparatuses for reset conditioning in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/601411 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6373 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594211.pdf [firstpage_image] =>[orig_patent_app_number] => 11601411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601411
Methods and apparatuses for reset conditioning in integrated circuits Nov 16, 2006 Issued
Array ( [id] => 340636 [patent_doc_number] => 07506294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Incremental solver for modeling an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/601601 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506294.pdf [firstpage_image] =>[orig_patent_app_number] => 11601601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601601
Incremental solver for modeling an integrated circuit Nov 16, 2006 Issued
Array ( [id] => 4470385 [patent_doc_number] => 07882457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-01 [patent_title] => 'DSP design system level power estimation' [patent_app_type] => utility [patent_app_number] => 11/600436 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882457.pdf [firstpage_image] =>[orig_patent_app_number] => 11600436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600436
DSP design system level power estimation Nov 14, 2006 Issued
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