
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5242385
[patent_doc_number] => 20070020880
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Method of fabricating a semiconductor device and a method of generating a mask pattern'
[patent_app_type] => utility
[patent_app_number] => 11/522995
[patent_app_country] => US
[patent_app_date] => 2006-09-19
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[pdf_file] => publications/A1/0020/20070020880.pdf
[firstpage_image] =>[orig_patent_app_number] => 11522995
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/522995 | Method of fabricating a semiconductor device and a method of generating a mask pattern | Sep 18, 2006 | Issued |
Array
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[patent_doc_number] => 20080072187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'Method, system, and program product for pre-compile processing of HDL source files'
[patent_app_type] => utility
[patent_app_number] => 11/521917
[patent_app_country] => US
[patent_app_date] => 2006-09-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/521917 | Method, system, and program product for pre-compile processing of hardware design language (HDL) source files | Sep 15, 2006 | Issued |
Array
(
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[patent_doc_number] => 07761829
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[patent_issue_date] => 2010-07-20
[patent_title] => 'Graphical specification of relative placement of circuit cells for repetitive circuit structures'
[patent_app_type] => utility
[patent_app_number] => 11/518921
[patent_app_country] => US
[patent_app_date] => 2006-09-12
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/518921 | Graphical specification of relative placement of circuit cells for repetitive circuit structures | Sep 11, 2006 | Issued |
Array
(
[id] => 49077
[patent_doc_number] => 07779381
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[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Test generation for low power circuits'
[patent_app_type] => utility
[patent_app_number] => 11/519381
[patent_app_country] => US
[patent_app_date] => 2006-09-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/519381 | Test generation for low power circuits | Sep 10, 2006 | Issued |
Array
(
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[patent_title] => 'Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master'
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[firstpage_image] =>[orig_patent_app_number] => 11468031
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468031 | Method for replicating and synchronizing a plurality of physical instances with a logical master | Aug 28, 2006 | Issued |
Array
(
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[patent_doc_number] => 20060277514
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[patent_title] => 'Method and System for Distributing Clock Signals on Non-Manhattan Semiconductor Integrated Circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/464478 | Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits | Aug 13, 2006 | Issued |
Array
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[patent_doc_number] => 07890910
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[patent_title] => 'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers'
[patent_app_type] => utility
[patent_app_number] => 11/499451
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/499451 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Aug 3, 2006 | Issued |
Array
(
[id] => 201054
[patent_doc_number] => 07640519
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[patent_kind] => B2
[patent_issue_date] => 2009-12-29
[patent_title] => 'Method and apparatus for automated synthesis of multi-channel circuits'
[patent_app_type] => utility
[patent_app_number] => 11/491437
[patent_app_country] => US
[patent_app_date] => 2006-07-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/491437 | Method and apparatus for automated synthesis of multi-channel circuits | Jul 20, 2006 | Issued |
Array
(
[id] => 5644349
[patent_doc_number] => 20060282804
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[patent_issue_date] => 2006-12-14
[patent_title] => 'NOVEL TEST STRUCTURE FOR AUTOMATIC DYNAMIC NEGATIVE-BIAS TEMPERATURE INSTABILITY TESTING'
[patent_app_type] => utility
[patent_app_number] => 11/458345
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458345 | Test structure for automatic dynamic negative-bias temperature instability testing | Jul 17, 2006 | Issued |
Array
(
[id] => 329775
[patent_doc_number] => 07516436
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[patent_issue_date] => 2009-04-07
[patent_title] => 'Method for manufacturing a power bus on a chip'
[patent_app_type] => utility
[patent_app_number] => 11/483638
[patent_app_country] => US
[patent_app_date] => 2006-07-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/483638 | Method for manufacturing a power bus on a chip | Jul 10, 2006 | Issued |
Array
(
[id] => 5663231
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[patent_title] => 'HIERARCHIAL SEMICONDUCTOR DESIGN'
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Array
(
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Array
(
[id] => 5139005
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Array
(
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[patent_title] => 'Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device'
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Array
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Array
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[id] => 5610379
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420371 | Circuit diagram drafting system and method and computer program product | May 24, 2006 | Issued |