Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5242385 [patent_doc_number] => 20070020880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method of fabricating a semiconductor device and a method of generating a mask pattern' [patent_app_type] => utility [patent_app_number] => 11/522995 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9290 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020880.pdf [firstpage_image] =>[orig_patent_app_number] => 11522995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/522995
Method of fabricating a semiconductor device and a method of generating a mask pattern Sep 18, 2006 Issued
Array ( [id] => 4923870 [patent_doc_number] => 20080072187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Method, system, and program product for pre-compile processing of HDL source files' [patent_app_type] => utility [patent_app_number] => 11/521917 [patent_app_country] => US [patent_app_date] => 2006-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072187.pdf [firstpage_image] =>[orig_patent_app_number] => 11521917 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521917
Method, system, and program product for pre-compile processing of hardware design language (HDL) source files Sep 15, 2006 Issued
Array ( [id] => 69216 [patent_doc_number] => 07761829 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Graphical specification of relative placement of circuit cells for repetitive circuit structures' [patent_app_type] => utility [patent_app_number] => 11/518921 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4416 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761829.pdf [firstpage_image] =>[orig_patent_app_number] => 11518921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518921
Graphical specification of relative placement of circuit cells for repetitive circuit structures Sep 11, 2006 Issued
Array ( [id] => 49077 [patent_doc_number] => 07779381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Test generation for low power circuits' [patent_app_type] => utility [patent_app_number] => 11/519381 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6366 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779381.pdf [firstpage_image] =>[orig_patent_app_number] => 11519381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519381
Test generation for low power circuits Sep 10, 2006 Issued
Array ( [id] => 4774290 [patent_doc_number] => 20080059952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master' [patent_app_type] => utility [patent_app_number] => 11/468031 [patent_app_country] => US [patent_app_date] => 2006-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059952.pdf [firstpage_image] =>[orig_patent_app_number] => 11468031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/468031
Method for replicating and synchronizing a plurality of physical instances with a logical master Aug 28, 2006 Issued
Array ( [id] => 5892187 [patent_doc_number] => 20060277514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Method and System for Distributing Clock Signals on Non-Manhattan Semiconductor Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/464478 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 5288 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277514.pdf [firstpage_image] =>[orig_patent_app_number] => 11464478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464478
Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits Aug 13, 2006 Issued
Array ( [id] => 4558601 [patent_doc_number] => 07890910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers' [patent_app_type] => utility [patent_app_number] => 11/499451 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890910.pdf [firstpage_image] =>[orig_patent_app_number] => 11499451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499451
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers Aug 3, 2006 Issued
Array ( [id] => 201054 [patent_doc_number] => 07640519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method and apparatus for automated synthesis of multi-channel circuits' [patent_app_type] => utility [patent_app_number] => 11/491437 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10082 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640519.pdf [firstpage_image] =>[orig_patent_app_number] => 11491437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/491437
Method and apparatus for automated synthesis of multi-channel circuits Jul 20, 2006 Issued
Array ( [id] => 5644349 [patent_doc_number] => 20060282804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'NOVEL TEST STRUCTURE FOR AUTOMATIC DYNAMIC NEGATIVE-BIAS TEMPERATURE INSTABILITY TESTING' [patent_app_type] => utility [patent_app_number] => 11/458345 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3928 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282804.pdf [firstpage_image] =>[orig_patent_app_number] => 11458345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458345
Test structure for automatic dynamic negative-bias temperature instability testing Jul 17, 2006 Issued
Array ( [id] => 329775 [patent_doc_number] => 07516436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method for manufacturing a power bus on a chip' [patent_app_type] => utility [patent_app_number] => 11/483638 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516436.pdf [firstpage_image] =>[orig_patent_app_number] => 11483638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483638
Method for manufacturing a power bus on a chip Jul 10, 2006 Issued
Array ( [id] => 5663231 [patent_doc_number] => 20060253827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'HIERARCHIAL SEMICONDUCTOR DESIGN' [patent_app_type] => utility [patent_app_number] => 11/428644 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9064 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253827.pdf [firstpage_image] =>[orig_patent_app_number] => 11428644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428644
HIERARCHIAL SEMICONDUCTOR DESIGN Jul 4, 2006 Abandoned
Array ( [id] => 5663213 [patent_doc_number] => 20060253809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'HIERARCHIAL SEMICONDUCTOR DESIGN' [patent_app_type] => utility [patent_app_number] => 11/428639 [patent_app_country] => US [patent_app_date] => 2006-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8955 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253809.pdf [firstpage_image] =>[orig_patent_app_number] => 11428639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/428639
HIERARCHIAL SEMICONDUCTOR DESIGN Jul 4, 2006 Abandoned
Array ( [id] => 5139005 [patent_doc_number] => 20070001221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Apparatus and method for generating transistor model' [patent_app_type] => utility [patent_app_number] => 11/478581 [patent_app_country] => US [patent_app_date] => 2006-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5974 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001221.pdf [firstpage_image] =>[orig_patent_app_number] => 11478581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478581
Apparatus and method for generating transistor model Jul 2, 2006 Issued
Array ( [id] => 5143899 [patent_doc_number] => 20070006115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/472441 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006115.pdf [firstpage_image] =>[orig_patent_app_number] => 11472441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472441
Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device Jun 21, 2006 Issued
Array ( [id] => 5200874 [patent_doc_number] => 20070300192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Method for Optimizing of Pipeline Structure Placement' [patent_app_type] => utility [patent_app_number] => 11/425721 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300192.pdf [firstpage_image] =>[orig_patent_app_number] => 11425721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425721
Method for optimizing of pipeline structure placement Jun 21, 2006 Issued
Array ( [id] => 5610379 [patent_doc_number] => 20060271895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Non-Uniform Decoupling Capacitor Distribution for Uniform Noise Reduction Across Chip' [patent_app_type] => utility [patent_app_number] => 11/421307 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6093 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271895.pdf [firstpage_image] =>[orig_patent_app_number] => 11421307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421307
Non-uniform decoupling capacitor distribution for uniform noise reduction across chip May 30, 2006 Issued
Array ( [id] => 372205 [patent_doc_number] => 07478344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-13 [patent_title] => 'Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms' [patent_app_type] => utility [patent_app_number] => 11/443906 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7083 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/478/07478344.pdf [firstpage_image] =>[orig_patent_app_number] => 11443906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/443906
Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms May 30, 2006 Issued
Array ( [id] => 5012818 [patent_doc_number] => 20070283297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Signal processing circuit' [patent_app_type] => utility [patent_app_number] => 11/443491 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9329 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283297.pdf [firstpage_image] =>[orig_patent_app_number] => 11443491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/443491
Signal processing circuit May 29, 2006 Abandoned
Array ( [id] => 5012832 [patent_doc_number] => 20070283311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Method and system for dynamic reconfiguration of field programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 11/442771 [patent_app_country] => US [patent_app_date] => 2006-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283311.pdf [firstpage_image] =>[orig_patent_app_number] => 11442771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/442771
Method and system for dynamic reconfiguration of field programmable gate arrays May 29, 2006 Abandoned
Array ( [id] => 5006681 [patent_doc_number] => 20070204254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'CIRCUIT DIAGRAM DRAFTING SYSTEM AND METHOD AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 11/420371 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9775 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204254.pdf [firstpage_image] =>[orig_patent_app_number] => 11420371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420371
Circuit diagram drafting system and method and computer program product May 24, 2006 Issued
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