Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5782365 [patent_doc_number] => 20060203580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Programmable element latch circuit' [patent_app_type] => utility [patent_app_number] => 11/436550 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203580.pdf [firstpage_image] =>[orig_patent_app_number] => 11436550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436550
Programmable element latch circuit May 18, 2006 Abandoned
Array ( [id] => 118493 [patent_doc_number] => 07716624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Mask creation with hierarchy management using cover cells' [patent_app_type] => utility [patent_app_number] => 11/438031 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4181 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716624.pdf [firstpage_image] =>[orig_patent_app_number] => 11438031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438031
Mask creation with hierarchy management using cover cells May 18, 2006 Issued
Array ( [id] => 5030088 [patent_doc_number] => 20070271535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Method for crosstalk elimination and bus architecture performing the same' [patent_app_type] => utility [patent_app_number] => 11/434961 [patent_app_country] => US [patent_app_date] => 2006-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7746 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271535.pdf [firstpage_image] =>[orig_patent_app_number] => 11434961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/434961
Method for crosstalk elimination and bus architecture performing the same May 15, 2006 Abandoned
Array ( [id] => 248938 [patent_doc_number] => 07587699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Automated system for designing and developing field programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 11/432186 [patent_app_country] => US [patent_app_date] => 2006-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 10460 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587699.pdf [firstpage_image] =>[orig_patent_app_number] => 11432186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/432186
Automated system for designing and developing field programmable gate arrays May 9, 2006 Issued
Array ( [id] => 5047675 [patent_doc_number] => 20070266349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'DIRECTED RANDOM VERIFICATION' [patent_app_type] => utility [patent_app_number] => 11/382371 [patent_app_country] => US [patent_app_date] => 2006-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266349.pdf [firstpage_image] =>[orig_patent_app_number] => 11382371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382371
DIRECTED RANDOM VERIFICATION May 8, 2006 Abandoned
Array ( [id] => 4804897 [patent_doc_number] => 20080016486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'System and method of assessing reliability of a semiconductor' [patent_app_type] => utility [patent_app_number] => 11/417451 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3903 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016486.pdf [firstpage_image] =>[orig_patent_app_number] => 11417451 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/417451
System and method of assessing reliability of a semiconductor May 2, 2006 Abandoned
Array ( [id] => 5706764 [patent_doc_number] => 20060195812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Designing system and method for designing a system LSI' [patent_app_type] => utility [patent_app_number] => 11/414221 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195812.pdf [firstpage_image] =>[orig_patent_app_number] => 11414221 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414221
Designing system and method for designing a system LSI Apr 30, 2006 Issued
Array ( [id] => 375065 [patent_doc_number] => 07475373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method and apparatus to visually assist legalized placement with non-uniform placement rules' [patent_app_type] => utility [patent_app_number] => 11/379411 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6424 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475373.pdf [firstpage_image] =>[orig_patent_app_number] => 11379411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379411
Method and apparatus to visually assist legalized placement with non-uniform placement rules Apr 19, 2006 Issued
Array ( [id] => 594649 [patent_doc_number] => 07461360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Validating very large network simulation results' [patent_app_type] => utility [patent_app_number] => 11/279391 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7421 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461360.pdf [firstpage_image] =>[orig_patent_app_number] => 11279391 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279391
Validating very large network simulation results Apr 10, 2006 Issued
Array ( [id] => 343372 [patent_doc_number] => 07503027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Hardware description language code generation from a state diagram' [patent_app_type] => utility [patent_app_number] => 11/394541 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 8895 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/503/07503027.pdf [firstpage_image] =>[orig_patent_app_number] => 11394541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394541
Hardware description language code generation from a state diagram Mar 30, 2006 Issued
Array ( [id] => 375073 [patent_doc_number] => 07475381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Shallow trench avoidance in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/394621 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4949 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475381.pdf [firstpage_image] =>[orig_patent_app_number] => 11394621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394621
Shallow trench avoidance in integrated circuits Mar 29, 2006 Issued
Array ( [id] => 107085 [patent_doc_number] => 07730432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective' [patent_app_type] => utility [patent_app_number] => 11/391771 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6708 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730432.pdf [firstpage_image] =>[orig_patent_app_number] => 11391771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/391771
Method and system for reshaping a transistor gate in an integrated circuit to achieve a target objective Mar 27, 2006 Issued
Array ( [id] => 874133 [patent_doc_number] => 07367009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Convergence technique for model-based optical and process correction' [patent_app_type] => utility [patent_app_number] => 11/388783 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4883 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/367/07367009.pdf [firstpage_image] =>[orig_patent_app_number] => 11388783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388783
Convergence technique for model-based optical and process correction Mar 23, 2006 Issued
Array ( [id] => 4592223 [patent_doc_number] => 07836417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-16 [patent_title] => 'Method and apparatus for parallel carry chains' [patent_app_type] => utility [patent_app_number] => 11/388326 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5559 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836417.pdf [firstpage_image] =>[orig_patent_app_number] => 11388326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388326
Method and apparatus for parallel carry chains Mar 22, 2006 Issued
Array ( [id] => 321674 [patent_doc_number] => 07523436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign' [patent_app_type] => utility [patent_app_number] => 11/385767 [patent_app_country] => US [patent_app_date] => 2006-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 34 [patent_no_of_words] => 10041 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523436.pdf [firstpage_image] =>[orig_patent_app_number] => 11385767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385767
Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign Mar 21, 2006 Issued
Array ( [id] => 5621369 [patent_doc_number] => 20060190904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Common interface framework for developing field programmable device based applications independent of a target circuit board' [patent_app_type] => utility [patent_app_number] => 11/385192 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190904.pdf [firstpage_image] =>[orig_patent_app_number] => 11385192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385192
Common interface framework for developing field programmable device based applications independent of a target circuit board Mar 20, 2006 Issued
Array ( [id] => 4979228 [patent_doc_number] => 20070220463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Inspection system' [patent_app_type] => utility [patent_app_number] => 11/378131 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1554 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220463.pdf [firstpage_image] =>[orig_patent_app_number] => 11378131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/378131
Inspection system Mar 16, 2006 Issued
Array ( [id] => 5621373 [patent_doc_number] => 20060190908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Coding of FPGA and standard cell logic in a tiling structure' [patent_app_type] => utility [patent_app_number] => 11/375891 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2251 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190908.pdf [firstpage_image] =>[orig_patent_app_number] => 11375891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375891
Coding of FPGA and standard cell logic in a tiling structure Mar 14, 2006 Abandoned
Array ( [id] => 258240 [patent_doc_number] => 07577928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Verification of an extracted timing model file' [patent_app_type] => utility [patent_app_number] => 11/376781 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4576 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577928.pdf [firstpage_image] =>[orig_patent_app_number] => 11376781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376781
Verification of an extracted timing model file Mar 14, 2006 Issued
Array ( [id] => 280196 [patent_doc_number] => 07559040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Optimization of combinational logic synthesis through clock latency scheduling' [patent_app_type] => utility [patent_app_number] => 11/373670 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 9097 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/559/07559040.pdf [firstpage_image] =>[orig_patent_app_number] => 11373670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/373670
Optimization of combinational logic synthesis through clock latency scheduling Mar 9, 2006 Issued
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