
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5782365
[patent_doc_number] => 20060203580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-14
[patent_title] => 'Programmable element latch circuit'
[patent_app_type] => utility
[patent_app_number] => 11/436550
[patent_app_country] => US
[patent_app_date] => 2006-05-19
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[pdf_file] => publications/A1/0203/20060203580.pdf
[firstpage_image] =>[orig_patent_app_number] => 11436550
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/436550 | Programmable element latch circuit | May 18, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 07716624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Mask creation with hierarchy management using cover cells'
[patent_app_type] => utility
[patent_app_number] => 11/438031
[patent_app_country] => US
[patent_app_date] => 2006-05-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438031 | Mask creation with hierarchy management using cover cells | May 18, 2006 | Issued |
Array
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[patent_doc_number] => 20070271535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-22
[patent_title] => 'Method for crosstalk elimination and bus architecture performing the same'
[patent_app_type] => utility
[patent_app_number] => 11/434961
[patent_app_country] => US
[patent_app_date] => 2006-05-16
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Array
(
[id] => 248938
[patent_doc_number] => 07587699
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[patent_kind] => B2
[patent_issue_date] => 2009-09-08
[patent_title] => 'Automated system for designing and developing field programmable gate arrays'
[patent_app_type] => utility
[patent_app_number] => 11/432186
[patent_app_country] => US
[patent_app_date] => 2006-05-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/432186 | Automated system for designing and developing field programmable gate arrays | May 9, 2006 | Issued |
Array
(
[id] => 5047675
[patent_doc_number] => 20070266349
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[patent_kind] => A1
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[patent_title] => 'DIRECTED RANDOM VERIFICATION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/382371 | DIRECTED RANDOM VERIFICATION | May 8, 2006 | Abandoned |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'System and method of assessing reliability of a semiconductor'
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Array
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[patent_app_date] => 2006-05-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/414221 | Designing system and method for designing a system LSI | Apr 30, 2006 | Issued |
Array
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[patent_issue_date] => 2009-01-06
[patent_title] => 'Method and apparatus to visually assist legalized placement with non-uniform placement rules'
[patent_app_type] => utility
[patent_app_number] => 11/379411
[patent_app_country] => US
[patent_app_date] => 2006-04-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/379411 | Method and apparatus to visually assist legalized placement with non-uniform placement rules | Apr 19, 2006 | Issued |
Array
(
[id] => 594649
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[patent_title] => 'Validating very large network simulation results'
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Array
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[patent_title] => 'Hardware description language code generation from a state diagram'
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Array
(
[id] => 375073
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[patent_title] => 'Shallow trench avoidance in integrated circuits'
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Array
(
[id] => 107085
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Array
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Array
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Array
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Array
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