Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5701832 [patent_doc_number] => 20060218517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method for designing integrated circuits comprising replacement logic gates' [patent_app_type] => utility [patent_app_number] => 11/360411 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3225 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218517.pdf [firstpage_image] =>[orig_patent_app_number] => 11360411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360411
Method for designing integrated circuits comprising replacement logic gates Feb 23, 2006 Issued
Array ( [id] => 5621363 [patent_doc_number] => 20060190898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing' [patent_app_type] => utility [patent_app_number] => 11/358101 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6686 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190898.pdf [firstpage_image] =>[orig_patent_app_number] => 11358101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358101
Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing Feb 21, 2006 Issued
Array ( [id] => 5115048 [patent_doc_number] => 20070198964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Multi-dimensional analysis for predicting RET model accuracy' [patent_app_type] => utility [patent_app_number] => 11/357431 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198964.pdf [firstpage_image] =>[orig_patent_app_number] => 11357431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357431
Multi-dimensional analysis for predicting RET model accuracy Feb 16, 2006 Issued
Array ( [id] => 336983 [patent_doc_number] => 07509612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method of designing semiconductor chip and program for use in designing semiconductor chip' [patent_app_type] => utility [patent_app_number] => 11/357641 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4372 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509612.pdf [firstpage_image] =>[orig_patent_app_number] => 11357641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357641
Method of designing semiconductor chip and program for use in designing semiconductor chip Feb 15, 2006 Issued
Array ( [id] => 5917035 [patent_doc_number] => 20060129953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Method for verifying and representing hardware by decomposition and partitioning' [patent_app_type] => utility [patent_app_number] => 11/352852 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12606 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129953.pdf [firstpage_image] =>[orig_patent_app_number] => 11352852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352852
Method for verifying and representing hardware by decomposition and partitioning Feb 12, 2006 Issued
Array ( [id] => 47951 [patent_doc_number] => 07784001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Circuit design method, circuit design system, and program product for causing computer to perform circuit design' [patent_app_type] => utility [patent_app_number] => 11/352231 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3478 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784001.pdf [firstpage_image] =>[orig_patent_app_number] => 11352231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/352231
Circuit design method, circuit design system, and program product for causing computer to perform circuit design Feb 12, 2006 Issued
Array ( [id] => 5102936 [patent_doc_number] => 20070186198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Generation of an extracted timing model file' [patent_app_type] => utility [patent_app_number] => 11/351091 [patent_app_country] => US [patent_app_date] => 2006-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3301 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20070186198.pdf [firstpage_image] =>[orig_patent_app_number] => 11351091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/351091
Generation of an extracted timing model file Feb 8, 2006 Issued
Array ( [id] => 5679552 [patent_doc_number] => 20060184908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method and program for generating layout data of a semiconductor integrated circuit and method for manufacturing a semiconductor integrated circuit with optical proximity correction' [patent_app_type] => utility [patent_app_number] => 11/347771 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184908.pdf [firstpage_image] =>[orig_patent_app_number] => 11347771 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347771
Method and program for generating layout data of a semiconductor integrated circuit and method for manufacturing a semiconductor integrated circuit with optical proximity correction Feb 2, 2006 Issued
Array ( [id] => 820193 [patent_doc_number] => 07412668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Integrated system noise management—decoupling capacitance' [patent_app_type] => utility [patent_app_number] => 11/343461 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 51 [patent_no_of_words] => 25788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412668.pdf [firstpage_image] =>[orig_patent_app_number] => 11343461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/343461
Integrated system noise management—decoupling capacitance Jan 29, 2006 Issued
Array ( [id] => 5847392 [patent_doc_number] => 20060123375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Integrated circuit capable of locating failure process layers' [patent_app_type] => utility [patent_app_number] => 11/341481 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2845 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123375.pdf [firstpage_image] =>[orig_patent_app_number] => 11341481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341481
Integrated circuit capable of locating failure process layers Jan 29, 2006 Issued
Array ( [id] => 375069 [patent_doc_number] => 07475377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Semiconductor device design system and method, and software product for the same' [patent_app_type] => utility [patent_app_number] => 11/341581 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 12607 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475377.pdf [firstpage_image] =>[orig_patent_app_number] => 11341581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/341581
Semiconductor device design system and method, and software product for the same Jan 29, 2006 Issued
Array ( [id] => 171995 [patent_doc_number] => 07669163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-23 [patent_title] => 'Partial configuration of a programmable gate array using a bus macro and coupling the third design' [patent_app_type] => utility [patent_app_number] => 11/338360 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5227 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669163.pdf [firstpage_image] =>[orig_patent_app_number] => 11338360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/338360
Partial configuration of a programmable gate array using a bus macro and coupling the third design Jan 23, 2006 Issued
Array ( [id] => 4929050 [patent_doc_number] => 20080168413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Method for Analyzing Component Mounting Board' [patent_app_type] => utility [patent_app_number] => 11/885831 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15101 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168413.pdf [firstpage_image] =>[orig_patent_app_number] => 11885831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/885831
Method for analyzing component mounting board Jan 19, 2006 Issued
Array ( [id] => 47962 [patent_doc_number] => 07784008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Performance visualization system' [patent_app_type] => utility [patent_app_number] => 11/330931 [patent_app_country] => US [patent_app_date] => 2006-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4971 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784008.pdf [firstpage_image] =>[orig_patent_app_number] => 11330931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/330931
Performance visualization system Jan 10, 2006 Issued
Array ( [id] => 5178700 [patent_doc_number] => 20070179760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Method of determining graph isomorphism in polynomial-time' [patent_app_type] => utility [patent_app_number] => 11/326971 [patent_app_country] => US [patent_app_date] => 2006-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11782 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20070179760.pdf [firstpage_image] =>[orig_patent_app_number] => 11326971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/326971
Method of determining graph isomorphism in polynomial-time Jan 5, 2006 Abandoned
Array ( [id] => 5161542 [patent_doc_number] => 20070174586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Processor controlled interface' [patent_app_type] => utility [patent_app_number] => 11/321836 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19404 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174586.pdf [firstpage_image] =>[orig_patent_app_number] => 11321836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321836
Generating interface adjustment signals in a device-to-device interconnection system Dec 28, 2005 Issued
Array ( [id] => 4990811 [patent_doc_number] => 20070157152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction' [patent_app_type] => utility [patent_app_number] => 11/323401 [patent_app_country] => US [patent_app_date] => 2005-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5451 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157152.pdf [firstpage_image] =>[orig_patent_app_number] => 11323401 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323401
Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction Dec 28, 2005 Issued
Array ( [id] => 116841 [patent_doc_number] => 07721242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Nanotube circuit analysis system and method' [patent_app_type] => utility [patent_app_number] => 11/314751 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3166 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721242.pdf [firstpage_image] =>[orig_patent_app_number] => 11314751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314751
Nanotube circuit analysis system and method Dec 19, 2005 Issued
Array ( [id] => 5651113 [patent_doc_number] => 20060136848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/305191 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11324 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136848.pdf [firstpage_image] =>[orig_patent_app_number] => 11305191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305191
Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit Dec 18, 2005 Issued
Array ( [id] => 245220 [patent_doc_number] => 07590964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Method and system for automatic generation of processor datapaths using instruction set architecture implementing means' [patent_app_type] => utility [patent_app_number] => 11/313231 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9645 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590964.pdf [firstpage_image] =>[orig_patent_app_number] => 11313231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313231
Method and system for automatic generation of processor datapaths using instruction set architecture implementing means Dec 18, 2005 Issued
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