Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 816693 [patent_doc_number] => 07415683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method and apparatus for a chaotic computing module' [patent_app_type] => utility [patent_app_number] => 11/304125 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415683.pdf [firstpage_image] =>[orig_patent_app_number] => 11304125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/304125
Method and apparatus for a chaotic computing module Dec 14, 2005 Issued
Array ( [id] => 825725 [patent_doc_number] => 07406669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models' [patent_app_type] => utility [patent_app_number] => 11/295351 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2900 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/406/07406669.pdf [firstpage_image] =>[orig_patent_app_number] => 11295351 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/295351
Timing constraints methodology for enabling clock reconvergence pessimism removal in extracted timing models Dec 5, 2005 Issued
Array ( [id] => 5848534 [patent_doc_number] => 20060231833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'High-Frequency, High-Signal-Density, Surface-Mount Technology Footprint Definitions' [patent_app_type] => utility [patent_app_number] => 11/287951 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 4425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20060231833.pdf [firstpage_image] =>[orig_patent_app_number] => 11287951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287951
High-frequency, high-signal-density, surface-mount technology footprint definitions Nov 27, 2005 Issued
Array ( [id] => 5749423 [patent_doc_number] => 20060112358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'System and method for designing a delayer emulation model' [patent_app_type] => utility [patent_app_number] => 11/285661 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1674 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20060112358.pdf [firstpage_image] =>[orig_patent_app_number] => 11285661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285661
System and method for designing a delayer emulation model Nov 20, 2005 Issued
Array ( [id] => 922267 [patent_doc_number] => 07325209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Using patterns for high-level modeling and specification of properties for hardware systems' [patent_app_type] => utility [patent_app_number] => 11/282071 [patent_app_country] => US [patent_app_date] => 2005-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6838 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325209.pdf [firstpage_image] =>[orig_patent_app_number] => 11282071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/282071
Using patterns for high-level modeling and specification of properties for hardware systems Nov 16, 2005 Issued
Array ( [id] => 600490 [patent_doc_number] => 07437700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Automated processor generation system and method for designing a configurable processor' [patent_app_type] => utility [patent_app_number] => 11/281217 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 28099 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437700.pdf [firstpage_image] =>[orig_patent_app_number] => 11281217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/281217
Automated processor generation system and method for designing a configurable processor Nov 15, 2005 Issued
Array ( [id] => 5867296 [patent_doc_number] => 20060101428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Compressing integrated circuit design data files' [patent_app_type] => utility [patent_app_number] => 11/272201 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5172 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101428.pdf [firstpage_image] =>[orig_patent_app_number] => 11272201 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/272201
Compressing integrated circuit design data files Nov 8, 2005 Abandoned
Array ( [id] => 313461 [patent_doc_number] => 07530033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Method and apparatus for decomposing functions in a configurable IC' [patent_app_type] => utility [patent_app_number] => 11/269141 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 51 [patent_no_of_words] => 18519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530033.pdf [firstpage_image] =>[orig_patent_app_number] => 11269141 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269141
Method and apparatus for decomposing functions in a configurable IC Nov 6, 2005 Issued
Array ( [id] => 213449 [patent_doc_number] => 07624368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Optimization of digital designs' [patent_app_type] => utility [patent_app_number] => 11/267587 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 17691 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/624/07624368.pdf [firstpage_image] =>[orig_patent_app_number] => 11267587 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267587
Optimization of digital designs Nov 3, 2005 Issued
Array ( [id] => 900365 [patent_doc_number] => 07343570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Methods, systems, and media to improve manufacturability of semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/265641 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7985 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343570.pdf [firstpage_image] =>[orig_patent_app_number] => 11265641 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265641
Methods, systems, and media to improve manufacturability of semiconductor devices Nov 1, 2005 Issued
Array ( [id] => 5712050 [patent_doc_number] => 20060053396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information' [patent_app_type] => utility [patent_app_number] => 11/262736 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10755 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20060053396.pdf [firstpage_image] =>[orig_patent_app_number] => 11262736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262736
Creating optimized physical implementations from high-level descriptions of electronic design using placement-based information Oct 31, 2005 Abandoned
Array ( [id] => 799199 [patent_doc_number] => 07428715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Hole query for functional coverage analysis' [patent_app_type] => utility [patent_app_number] => 11/260781 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8607 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428715.pdf [firstpage_image] =>[orig_patent_app_number] => 11260781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260781
Hole query for functional coverage analysis Oct 26, 2005 Issued
Array ( [id] => 5907447 [patent_doc_number] => 20060048086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Integrated circuit analysis method and program product' [patent_app_type] => utility [patent_app_number] => 11/261951 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5442 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20060048086.pdf [firstpage_image] =>[orig_patent_app_number] => 11261951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261951
Integrated circuit analysis method and program product Oct 26, 2005 Issued
Array ( [id] => 514022 [patent_doc_number] => 07207022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Layout design method for semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/255965 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/207/07207022.pdf [firstpage_image] =>[orig_patent_app_number] => 11255965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255965
Layout design method for semiconductor integrated circuits Oct 23, 2005 Issued
Array ( [id] => 5712058 [patent_doc_number] => 20060053404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Methods and apparatus for implementing parameterizable processors and peripherals' [patent_app_type] => utility [patent_app_number] => 11/256311 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8592 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11256311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256311
Methods and apparatus for implementing parameterizable processors and peripherals Oct 20, 2005 Issued
Array ( [id] => 5810773 [patent_doc_number] => 20060081881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Circuit wiring laying-out apparatus, method of laying-out a circuit, signal-bearing medium embodying a program of laying-out wiring, wiring layout, and method of using a wiring layout' [patent_app_type] => utility [patent_app_number] => 11/250581 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3904 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081881.pdf [firstpage_image] =>[orig_patent_app_number] => 11250581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250581
Circuit wiring laying-out apparatus, method of laying-out a circuit, signal-bearing medium embodying a program of laying-out wiring, wiring layout, and method of using a wiring layout Oct 16, 2005 Abandoned
Array ( [id] => 5758658 [patent_doc_number] => 20060209603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Method and apparatus for supporting verification, and computer product' [patent_app_type] => utility [patent_app_number] => 11/249361 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5715 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20060209603.pdf [firstpage_image] =>[orig_patent_app_number] => 11249361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249361
Method and apparatus for supporting verification, and computer product Oct 13, 2005 Issued
Array ( [id] => 599510 [patent_doc_number] => 07444601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Trusted computing platform' [patent_app_type] => utility [patent_app_number] => 11/249820 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6228 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444601.pdf [firstpage_image] =>[orig_patent_app_number] => 11249820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249820
Trusted computing platform Oct 11, 2005 Issued
Array ( [id] => 594654 [patent_doc_number] => 07461361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method' [patent_app_type] => utility [patent_app_number] => 11/247731 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461361.pdf [firstpage_image] =>[orig_patent_app_number] => 11247731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/247731
Method of creating core-tile-switch mapping architecture in on-chip bus and computer-readable medium for recording the method Oct 10, 2005 Issued
Array ( [id] => 462730 [patent_doc_number] => 07246333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Apparatus and method for unified debug for simulation' [patent_app_type] => utility [patent_app_number] => 11/248709 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4774 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246333.pdf [firstpage_image] =>[orig_patent_app_number] => 11248709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248709
Apparatus and method for unified debug for simulation Oct 10, 2005 Issued
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