| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 414986
[patent_doc_number] => 07284213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Defect analysis using a yield vehicle'
[patent_app_type] => utility
[patent_app_number] => 11/247517
[patent_app_country] => US
[patent_app_date] => 2005-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7983
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/284/07284213.pdf
[firstpage_image] =>[orig_patent_app_number] => 11247517
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/247517 | Defect analysis using a yield vehicle | Oct 10, 2005 | Issued |
Array
(
[id] => 137346
[patent_doc_number] => 07698665
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-13
[patent_title] => 'Systems, masks, and methods for manufacturable masks using a functional representation of polygon pattern'
[patent_app_type] => utility
[patent_app_number] => 11/245691
[patent_app_country] => US
[patent_app_date] => 2005-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 11144
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/698/07698665.pdf
[firstpage_image] =>[orig_patent_app_number] => 11245691
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/245691 | Systems, masks, and methods for manufacturable masks using a functional representation of polygon pattern | Oct 5, 2005 | Issued |
Array
(
[id] => 525939
[patent_doc_number] => 07197730
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-27
[patent_title] => 'Reducing time to design integrated circuits including performing electro-migration check'
[patent_app_type] => utility
[patent_app_number] => 11/163102
[patent_app_country] => US
[patent_app_date] => 2005-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2940
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/197/07197730.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163102
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163102 | Reducing time to design integrated circuits including performing electro-migration check | Oct 4, 2005 | Issued |
Array
(
[id] => 372206
[patent_doc_number] => 07478345
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-13
[patent_title] => 'Apparatus and method for measuring characteristics of dynamic electrical signals in integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/241609
[patent_app_country] => US
[patent_app_date] => 2005-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4577
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/478/07478345.pdf
[firstpage_image] =>[orig_patent_app_number] => 11241609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/241609 | Apparatus and method for measuring characteristics of dynamic electrical signals in integrated circuits | Sep 29, 2005 | Issued |
Array
(
[id] => 66679
[patent_doc_number] => 07765502
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-27
[patent_title] => 'ASIC functional specification parser'
[patent_app_type] => utility
[patent_app_number] => 11/241661
[patent_app_country] => US
[patent_app_date] => 2005-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2409
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/765/07765502.pdf
[firstpage_image] =>[orig_patent_app_number] => 11241661
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/241661 | ASIC functional specification parser | Sep 28, 2005 | Issued |
Array
(
[id] => 898535
[patent_doc_number] => 07346863
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-03-18
[patent_title] => 'Hardware acceleration of high-level language code sequences on programmable devices'
[patent_app_type] => utility
[patent_app_number] => 11/238451
[patent_app_country] => US
[patent_app_date] => 2005-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9407
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/346/07346863.pdf
[firstpage_image] =>[orig_patent_app_number] => 11238451
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/238451 | Hardware acceleration of high-level language code sequences on programmable devices | Sep 27, 2005 | Issued |
Array
(
[id] => 927571
[patent_doc_number] => 07318212
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-08
[patent_title] => 'Method and system for modeling wiring routing in a circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/232747
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 4257
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/318/07318212.pdf
[firstpage_image] =>[orig_patent_app_number] => 11232747
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232747 | Method and system for modeling wiring routing in a circuit design | Sep 21, 2005 | Issued |
Array
(
[id] => 895078
[patent_doc_number] => 07350180
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-03-25
[patent_title] => 'Search algorithm for inheriting clock contexts in hardware description language translation tools'
[patent_app_type] => utility
[patent_app_number] => 11/228991
[patent_app_country] => US
[patent_app_date] => 2005-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13510
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/350/07350180.pdf
[firstpage_image] =>[orig_patent_app_number] => 11228991
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/228991 | Search algorithm for inheriting clock contexts in hardware description language translation tools | Sep 16, 2005 | Issued |
Array
(
[id] => 905188
[patent_doc_number] => 07340705
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-03-04
[patent_title] => 'In-circuit device, system and method to parallelize design and verification of application-specific integrated circuits (“ASICs”) having embedded specialized function circuits'
[patent_app_type] => utility
[patent_app_number] => 11/229331
[patent_app_country] => US
[patent_app_date] => 2005-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4845
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/340/07340705.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229331
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229331 | In-circuit device, system and method to parallelize design and verification of application-specific integrated circuits (“ASICsâ€) having embedded specialized function circuits | Sep 15, 2005 | Issued |
Array
(
[id] => 478750
[patent_doc_number] => 07231622
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-12
[patent_title] => 'Method for correcting crosstalk'
[patent_app_type] => utility
[patent_app_number] => 11/226326
[patent_app_country] => US
[patent_app_date] => 2005-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 29
[patent_no_of_words] => 9326
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/231/07231622.pdf
[firstpage_image] =>[orig_patent_app_number] => 11226326
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226326 | Method for correcting crosstalk | Sep 14, 2005 | Issued |
Array
(
[id] => 898660
[patent_doc_number] => 07346884
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-03-18
[patent_title] => 'Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same'
[patent_app_type] => utility
[patent_app_number] => 11/226135
[patent_app_country] => US
[patent_app_date] => 2005-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3215
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/346/07346884.pdf
[firstpage_image] =>[orig_patent_app_number] => 11226135
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226135 | Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same | Sep 12, 2005 | Issued |
Array
(
[id] => 5150676
[patent_doc_number] => 20070050736
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'METHOD OF FACILITATING INTEGRATED CIRCUIT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 11/162196
[patent_app_country] => US
[patent_app_date] => 2005-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5061
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20070050736.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162196
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162196 | Method of facilitating integrated circuit design using manufactured property values | Aug 30, 2005 | Issued |
Array
(
[id] => 829407
[patent_doc_number] => 07404162
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-22
[patent_title] => 'Buffering technique using structured delay skewing'
[patent_app_type] => utility
[patent_app_number] => 11/211501
[patent_app_country] => US
[patent_app_date] => 2005-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3227
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/404/07404162.pdf
[firstpage_image] =>[orig_patent_app_number] => 11211501
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/211501 | Buffering technique using structured delay skewing | Aug 25, 2005 | Issued |
Array
(
[id] => 451431
[patent_doc_number] => 07254796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Method for synthesizing domino logic circuits cross reference to related patent application using partition'
[patent_app_type] => utility
[patent_app_number] => 11/208477
[patent_app_country] => US
[patent_app_date] => 2005-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5166
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/254/07254796.pdf
[firstpage_image] =>[orig_patent_app_number] => 11208477
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/208477 | Method for synthesizing domino logic circuits cross reference to related patent application using partition | Aug 18, 2005 | Issued |
Array
(
[id] => 599509
[patent_doc_number] => 07444600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'System and method for circuit noise analysis'
[patent_app_type] => utility
[patent_app_number] => 11/205421
[patent_app_country] => US
[patent_app_date] => 2005-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5097
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/444/07444600.pdf
[firstpage_image] =>[orig_patent_app_number] => 11205421
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205421 | System and method for circuit noise analysis | Aug 16, 2005 | Issued |
Array
(
[id] => 427994
[patent_doc_number] => 07272804
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-18
[patent_title] => 'Generation of RTL to carry out parallel arithmetic operations'
[patent_app_type] => utility
[patent_app_number] => 11/190879
[patent_app_country] => US
[patent_app_date] => 2005-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2452
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/272/07272804.pdf
[firstpage_image] =>[orig_patent_app_number] => 11190879
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/190879 | Generation of RTL to carry out parallel arithmetic operations | Jul 27, 2005 | Issued |
Array
(
[id] => 5774532
[patent_doc_number] => 20050268272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes'
[patent_app_type] => utility
[patent_app_number] => 11/184401
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4514
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0268/20050268272.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184401
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184401 | Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes | Jul 18, 2005 | Issued |
Array
(
[id] => 5744427
[patent_doc_number] => 20060090153
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Method and apparatus for reducing power consumption in an integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 11/182100
[patent_app_country] => US
[patent_app_date] => 2005-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3355
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20060090153.pdf
[firstpage_image] =>[orig_patent_app_number] => 11182100
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/182100 | Method and apparatus for reducing power consumption in an integrated circuit chip | Jul 13, 2005 | Issued |
Array
(
[id] => 261947
[patent_doc_number] => 07574681
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Method and system for evaluating computer program tests by means of mutation analysis'
[patent_app_type] => utility
[patent_app_number] => 11/631191
[patent_app_country] => US
[patent_app_date] => 2005-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4851
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/574/07574681.pdf
[firstpage_image] =>[orig_patent_app_number] => 11631191
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/631191 | Method and system for evaluating computer program tests by means of mutation analysis | Jul 11, 2005 | Issued |
Array
(
[id] => 421641
[patent_doc_number] => 07278125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-02
[patent_title] => 'Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method'
[patent_app_type] => utility
[patent_app_number] => 11/176181
[patent_app_country] => US
[patent_app_date] => 2005-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 4885
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/278/07278125.pdf
[firstpage_image] =>[orig_patent_app_number] => 11176181
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/176181 | Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method | Jul 7, 2005 | Issued |