Jeffrey T. Knapp

Array ( [id] => 375064 [patent_doc_number] => 07475372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Methods for computing Miller-factor using coupled peak noise' [patent_app_type] => utility [patent_app_number] => 11/160701 [patent_app_country] => US [patent_app_date] => 2005-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2375 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475372.pdf [firstpage_image] =>[orig_patent_app_number] => 11160701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5627168 [patent_doc_number] => 20060265673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Facilitating High Level Validation of Integrated Circuits in Parallel with Development of Blocks in a Hierarchical Design Approach' [patent_app_type] => utility [patent_app_number] => 11/160631 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265673.pdf [firstpage_image] =>[orig_patent_app_number] => 11160631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 587418 [patent_doc_number] => 07467362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method' [patent_app_type] => utility [patent_app_number] => 11/167281 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4414 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467362.pdf [firstpage_image] =>[orig_patent_app_number] => 11167281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 498642 [patent_doc_number] => 07216307 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Method of identifying state nodes at the transistor level in a sequential digital circuit using minimum combinatorial feedback loop' [patent_app_type] => utility [patent_app_number] => 11/167523 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4778 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216307.pdf [firstpage_image] =>[orig_patent_app_number] => 11167523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5604135 [patent_doc_number] => 20060294482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/165778 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5790 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294482.pdf [firstpage_image] =>[orig_patent_app_number] => 11165778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 447583 [patent_doc_number] => 07257798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method and system for designing a timing closure of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/156621 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3979 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257798.pdf [firstpage_image] =>[orig_patent_app_number] => 11156621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6975431 [patent_doc_number] => 20050285146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Semiconductor device, manufacturing method of the semiconductor device, and design method of the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/154631 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8254 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285146.pdf [firstpage_image] =>[orig_patent_app_number] => 11154631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5644354 [patent_doc_number] => 20060282809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Logic transformation and gate placement to avoid routing congestion' [patent_app_type] => utility [patent_app_number] => 11/153707 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4530 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282809.pdf [firstpage_image] =>[orig_patent_app_number] => 11153707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 398051 [patent_doc_number] => 07302661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Efficient electromagnetic modeling of irregular metal planes' [patent_app_type] => utility [patent_app_number] => 11/152580 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4149 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302661.pdf [firstpage_image] =>[orig_patent_app_number] => 11152580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 398032 [patent_doc_number] => 07302655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Method for verifying a circuit design by assigning numerical values to inputs of the circuit design' [patent_app_type] => utility [patent_app_number] => 11/152472 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3248 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302655.pdf [firstpage_image] =>[orig_patent_app_number] => 11152472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6954051 [patent_doc_number] => 20050229146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Data storage method and data storage device' [patent_app_type] => utility [patent_app_number] => 11/149261 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5614 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229146.pdf [firstpage_image] =>[orig_patent_app_number] => 11149261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7599893 [patent_doc_number] => 07386820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method and apparatus for formally checking equivalence using equivalence relationships' [patent_app_type] => utility [patent_app_number] => 11/149751 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 108 [patent_no_of_words] => 41382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386820.pdf [firstpage_image] =>[orig_patent_app_number] => 11149751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5615352 [patent_doc_number] => 20060117282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Method that allows flexible evaluation of power-gated circuits' [patent_app_type] => utility [patent_app_number] => 11/150031 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2786 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117282.pdf [firstpage_image] =>[orig_patent_app_number] => 11150031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5640416 [patent_doc_number] => 20060278871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Detecting and improving bond pad connectivity with pad check' [patent_app_type] => utility [patent_app_number] => 11/147541 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4818 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20060278871.pdf [firstpage_image] =>[orig_patent_app_number] => 11147541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5892195 [patent_doc_number] => 20060277517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Wire spreading through geotopological layout' [patent_app_type] => utility [patent_app_number] => 11/146485 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277517.pdf [firstpage_image] =>[orig_patent_app_number] => 11146485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5682814 [patent_doc_number] => 20060199084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Chromeless phase shifting mask for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/144157 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3541 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199084.pdf [firstpage_image] =>[orig_patent_app_number] => 11144157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 900371 [patent_doc_number] => 07343573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method and system for enhanced verification through binary decision diagram-based target decomposition' [patent_app_type] => utility [patent_app_number] => 11/143331 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8560 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343573.pdf [firstpage_image] =>[orig_patent_app_number] => 11143331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 466349 [patent_doc_number] => 07243315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arrays' [patent_app_type] => utility [patent_app_number] => 11/141941 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6405 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243315.pdf [firstpage_image] =>[orig_patent_app_number] => 11141941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5604727 [patent_doc_number] => 20060266243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Calibration on wafer sweet spots' [patent_app_type] => utility [patent_app_number] => 11/139551 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12033 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20060266243.pdf [firstpage_image] =>[orig_patent_app_number] => 11139551 [rel_patent_id] =>[rel_patent_doc_number] =>)