
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 379190
[patent_doc_number] => 07313772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-25
[patent_title] => 'Systems, methods, and media for block-based assertion generation, qualification and analysis'
[patent_app_type] => utility
[patent_app_number] => 11/136256
[patent_app_country] => US
[patent_app_date] => 2005-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9163
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/313/07313772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11136256
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/136256 | Systems, methods, and media for block-based assertion generation, qualification and analysis | May 23, 2005 | Issued |
Array
(
[id] => 7234255
[patent_doc_number] => 20050262469
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Method of calculating predictive shape of wiring structure, calculating apparatus, and computer-readable recording medium'
[patent_app_type] => utility
[patent_app_number] => 11/133261
[patent_app_country] => US
[patent_app_date] => 2005-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8496
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0262/20050262469.pdf
[firstpage_image] =>[orig_patent_app_number] => 11133261
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/133261 | Method of calculating predictive shape of wiring structure, calculating apparatus, and computer-readable recording medium | May 19, 2005 | Issued |
Array
(
[id] => 591177
[patent_doc_number] => 07464364
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-09
[patent_title] => 'Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device'
[patent_app_type] => utility
[patent_app_number] => 11/133321
[patent_app_country] => US
[patent_app_date] => 2005-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 8165
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/464/07464364.pdf
[firstpage_image] =>[orig_patent_app_number] => 11133321
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/133321 | Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device | May 19, 2005 | Issued |
Array
(
[id] => 5734770
[patent_doc_number] => 20060259887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells'
[patent_app_type] => utility
[patent_app_number] => 11/128069
[patent_app_country] => US
[patent_app_date] => 2005-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6619
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20060259887.pdf
[firstpage_image] =>[orig_patent_app_number] => 11128069
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/128069 | Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells | May 11, 2005 | Issued |
Array
(
[id] => 832774
[patent_doc_number] => 07401317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-07-15
[patent_title] => 'Method and system for rapidly identifying silicon manufacturing defects'
[patent_app_type] => utility
[patent_app_number] => 11/128861
[patent_app_country] => US
[patent_app_date] => 2005-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3441
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/401/07401317.pdf
[firstpage_image] =>[orig_patent_app_number] => 11128861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/128861 | Method and system for rapidly identifying silicon manufacturing defects | May 11, 2005 | Issued |
Array
(
[id] => 5734767
[patent_doc_number] => 20060259884
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Merging a hardware design language source file with a separate assertion file'
[patent_app_type] => utility
[patent_app_number] => 11/125991
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3844
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20060259884.pdf
[firstpage_image] =>[orig_patent_app_number] => 11125991
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/125991 | Merging a hardware design language source file with a separate assertion file | May 9, 2005 | Issued |
Array
(
[id] => 407409
[patent_doc_number] => 07290234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-30
[patent_title] => 'Method for computer aided design of semiconductor integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/122221
[patent_app_country] => US
[patent_app_date] => 2005-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5195
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/290/07290234.pdf
[firstpage_image] =>[orig_patent_app_number] => 11122221
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/122221 | Method for computer aided design of semiconductor integrated circuits | May 4, 2005 | Issued |
Array
(
[id] => 877907
[patent_doc_number] => 07363596
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-04-22
[patent_title] => 'Methods for storing and naming static library cells for lookup by logic synthesis and the like'
[patent_app_type] => utility
[patent_app_number] => 11/115641
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4615
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/363/07363596.pdf
[firstpage_image] =>[orig_patent_app_number] => 11115641
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/115641 | Methods for storing and naming static library cells for lookup by logic synthesis and the like | Apr 26, 2005 | Issued |
Array
(
[id] => 555844
[patent_doc_number] => 07181711
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Prioritizing of nets for coupled noise analysis'
[patent_app_type] => utility
[patent_app_number] => 10/908101
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4631
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/181/07181711.pdf
[firstpage_image] =>[orig_patent_app_number] => 10908101
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/908101 | Prioritizing of nets for coupled noise analysis | Apr 26, 2005 | Issued |
Array
(
[id] => 418403
[patent_doc_number] => 07281230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-09
[patent_title] => 'Method of using mixed multi-Vt devices in a cell-based design'
[patent_app_type] => utility
[patent_app_number] => 11/111281
[patent_app_country] => US
[patent_app_date] => 2005-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3173
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/281/07281230.pdf
[firstpage_image] =>[orig_patent_app_number] => 11111281
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/111281 | Method of using mixed multi-Vt devices in a cell-based design | Apr 19, 2005 | Issued |
Array
(
[id] => 27581
[patent_doc_number] => 07802212
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Processor controlled interface'
[patent_app_type] => utility
[patent_app_number] => 11/107121
[patent_app_country] => US
[patent_app_date] => 2005-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 15494
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/802/07802212.pdf
[firstpage_image] =>[orig_patent_app_number] => 11107121
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/107121 | Processor controlled interface | Apr 14, 2005 | Issued |
Array
(
[id] => 5836652
[patent_doc_number] => 20060248484
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Method for preserving constraints during sequential reparameterization'
[patent_app_type] => utility
[patent_app_number] => 11/105611
[patent_app_country] => US
[patent_app_date] => 2005-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 13899
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20060248484.pdf
[firstpage_image] =>[orig_patent_app_number] => 11105611
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/105611 | Method for preserving constraints during sequential reparameterization | Apr 13, 2005 | Issued |
Array
(
[id] => 6910799
[patent_doc_number] => 20050174557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'Exposure pattern forming method and exposure pattern'
[patent_app_type] => utility
[patent_app_number] => 11/101479
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5976
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20050174557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11101479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/101479 | Exposure pattern forming method and exposure pattern | Apr 7, 2005 | Issued |
Array
(
[id] => 435236
[patent_doc_number] => 07266796
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-04
[patent_title] => 'Fastplace method for integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/102381
[patent_app_country] => US
[patent_app_date] => 2005-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7527
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/266/07266796.pdf
[firstpage_image] =>[orig_patent_app_number] => 11102381
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/102381 | Fastplace method for integrated circuit design | Apr 7, 2005 | Issued |
Array
(
[id] => 905175
[patent_doc_number] => 07340695
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-04
[patent_title] => 'Reformulation of the finite-difference time-domain algorithm for hardware-based accelerators'
[patent_app_type] => utility
[patent_app_number] => 11/100861
[patent_app_country] => US
[patent_app_date] => 2005-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 4794
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/340/07340695.pdf
[firstpage_image] =>[orig_patent_app_number] => 11100861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/100861 | Reformulation of the finite-difference time-domain algorithm for hardware-based accelerators | Apr 6, 2005 | Issued |
Array
(
[id] => 481760
[patent_doc_number] => 07228511
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-05
[patent_title] => 'Method and apparatus for designing printed circuit boards to meet leakage current requirements'
[patent_app_type] => utility
[patent_app_number] => 11/094458
[patent_app_country] => US
[patent_app_date] => 2005-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2778
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/228/07228511.pdf
[firstpage_image] =>[orig_patent_app_number] => 11094458
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/094458 | Method and apparatus for designing printed circuit boards to meet leakage current requirements | Mar 29, 2005 | Issued |
Array
(
[id] => 6968396
[patent_doc_number] => 20050235232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Method and apparatus for designing and manufacturing electronic circuits subject to process variations'
[patent_app_type] => utility
[patent_app_number] => 11/095494
[patent_app_country] => US
[patent_app_date] => 2005-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 19809
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20050235232.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095494
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095494 | Method and apparatus for designing and manufacturing electronic circuits subject to process variations | Mar 29, 2005 | Issued |
Array
(
[id] => 856482
[patent_doc_number] => 07380224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Method and system for non-linear state based satisfiability'
[patent_app_type] => utility
[patent_app_number] => 11/090647
[patent_app_country] => US
[patent_app_date] => 2005-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10686
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/380/07380224.pdf
[firstpage_image] =>[orig_patent_app_number] => 11090647
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/090647 | Method and system for non-linear state based satisfiability | Mar 24, 2005 | Issued |
Array
(
[id] => 5861753
[patent_doc_number] => 20060230367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Method and system for reduction of and/or subexpressions in structural design representations'
[patent_app_type] => utility
[patent_app_number] => 11/086721
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 9879
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20060230367.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086721
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086721 | Method and system for reduction of and/or subexpressions in structural design representations | Mar 21, 2005 | Issued |
Array
(
[id] => 905172
[patent_doc_number] => 07340694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-04
[patent_title] => 'Method and system for reduction of XOR/XNOR subexpressions in structural design representations'
[patent_app_type] => utility
[patent_app_number] => 11/086720
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 9874
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/340/07340694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11086720
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/086720 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Mar 21, 2005 | Issued |