Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5861756 [patent_doc_number] => 20060230370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'System and method for engine-controlled case splitting within a multiple-engine based verification framework' [patent_app_type] => utility [patent_app_number] => 11/082699 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4137 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230370.pdf [firstpage_image] =>[orig_patent_app_number] => 11082699 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082699
System and method for engine-controlled case splitting within multiple-engine based verification framework Mar 16, 2005 Issued
Array ( [id] => 375070 [patent_doc_number] => 07475378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Method of designing semiconductor integrated circuit in which fault detection can be effected through scan-in and scan-out' [patent_app_type] => utility [patent_app_number] => 11/079292 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 26200 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475378.pdf [firstpage_image] =>[orig_patent_app_number] => 11079292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/079292
Method of designing semiconductor integrated circuit in which fault detection can be effected through scan-in and scan-out Mar 14, 2005 Issued
Array ( [id] => 5789316 [patent_doc_number] => 20060206842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method for retiming in the presence of verification constraints' [patent_app_type] => utility [patent_app_number] => 11/077331 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206842.pdf [firstpage_image] =>[orig_patent_app_number] => 11077331 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077331
Method for retiming in the presence of verification constraints Mar 9, 2005 Issued
Array ( [id] => 7042841 [patent_doc_number] => 20050160394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Driven inspection or measurement' [patent_app_type] => utility [patent_app_number] => 11/078261 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5865 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160394.pdf [firstpage_image] =>[orig_patent_app_number] => 11078261 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078261
Driven inspection or measurement Mar 9, 2005 Issued
Array ( [id] => 428000 [patent_doc_number] => 07272807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Determining equivalent waveforms for distorted waveforms' [patent_app_type] => utility [patent_app_number] => 11/071121 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5260 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272807.pdf [firstpage_image] =>[orig_patent_app_number] => 11071121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071121
Determining equivalent waveforms for distorted waveforms Mar 1, 2005 Issued
Array ( [id] => 7178582 [patent_doc_number] => 20050204330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Exposure pattern forming method and exposure pattern' [patent_app_type] => utility [patent_app_number] => 11/068922 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5973 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204330.pdf [firstpage_image] =>[orig_patent_app_number] => 11068922 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068922
Exposure pattern forming method and exposure pattern Mar 1, 2005 Issued
Array ( [id] => 5615360 [patent_doc_number] => 20060117290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Wiring method, program, and apparatus' [patent_app_type] => utility [patent_app_number] => 11/066461 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7720 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117290.pdf [firstpage_image] =>[orig_patent_app_number] => 11066461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066461
Wiring method, program, and apparatus Feb 27, 2005 Issued
Array ( [id] => 820209 [patent_doc_number] => 07412681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'DC path checking in a hierarchical circuit design' [patent_app_type] => utility [patent_app_number] => 11/067571 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12994 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412681.pdf [firstpage_image] =>[orig_patent_app_number] => 11067571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067571
DC path checking in a hierarchical circuit design Feb 24, 2005 Issued
Array ( [id] => 5706761 [patent_doc_number] => 20060195809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'CIRCUIT LAYOUT METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 10/906591 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4548 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195809.pdf [firstpage_image] =>[orig_patent_app_number] => 10906591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906591
Circuit layout methodology using a shape processing application Feb 24, 2005 Issued
Array ( [id] => 5621339 [patent_doc_number] => 20060190874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method and system for formal unidirectional bus verification' [patent_app_type] => utility [patent_app_number] => 11/065601 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190874.pdf [firstpage_image] =>[orig_patent_app_number] => 11065601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065601
Method and system for formal unidirectional bus verification using synthesizing constrained drivers Feb 23, 2005 Issued
Array ( [id] => 481773 [patent_doc_number] => 07228516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Negative bias temperature instability modeling' [patent_app_type] => utility [patent_app_number] => 11/061581 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1972 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228516.pdf [firstpage_image] =>[orig_patent_app_number] => 11061581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061581
Negative bias temperature instability modeling Feb 17, 2005 Issued
Array ( [id] => 7140960 [patent_doc_number] => 20050183053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Software product for and method of laying-out semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/059481 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20050183053.pdf [firstpage_image] =>[orig_patent_app_number] => 11059481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059481
Software product for and method of laying-out semiconductor device Feb 16, 2005 Abandoned
Array ( [id] => 7180482 [patent_doc_number] => 20050190702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Delay time verifying method with less processing load' [patent_app_type] => utility [patent_app_number] => 11/059311 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7066 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20050190702.pdf [firstpage_image] =>[orig_patent_app_number] => 11059311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/059311
Delay time verifying method with less processing load Feb 16, 2005 Issued
Array ( [id] => 498636 [patent_doc_number] => 07216306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Checkpoint restart method using condensed partial results by determining boolean constant subsets' [patent_app_type] => utility [patent_app_number] => 11/057651 [patent_app_country] => US [patent_app_date] => 2005-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216306.pdf [firstpage_image] =>[orig_patent_app_number] => 11057651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057651
Checkpoint restart method using condensed partial results by determining boolean constant subsets Feb 13, 2005 Issued
Array ( [id] => 388846 [patent_doc_number] => 07305635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'Serial implementation of assertion checking logic circuit' [patent_app_type] => utility [patent_app_number] => 11/051774 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4487 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305635.pdf [firstpage_image] =>[orig_patent_app_number] => 11051774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051774
Serial implementation of assertion checking logic circuit Feb 3, 2005 Issued
Array ( [id] => 5621352 [patent_doc_number] => 20060190887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'METHOD FOR REALIZING CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 10/906101 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2596 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190887.pdf [firstpage_image] =>[orig_patent_app_number] => 10906101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906101
Method for realizing circuit layout using cell library Feb 2, 2005 Issued
Array ( [id] => 869163 [patent_doc_number] => 07370312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-06 [patent_title] => 'System and method for controlling simulation of hardware in a hardware development process' [patent_app_type] => utility [patent_app_number] => 11/047281 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6505 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/370/07370312.pdf [firstpage_image] =>[orig_patent_app_number] => 11047281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/047281
System and method for controlling simulation of hardware in a hardware development process Jan 30, 2005 Issued
Array ( [id] => 7100737 [patent_doc_number] => 20050132318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Layout quality analyzer' [patent_app_type] => utility [patent_app_number] => 11/046071 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4461 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132318.pdf [firstpage_image] =>[orig_patent_app_number] => 11046071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046071
Layout quality analyzer Jan 27, 2005 Abandoned
Array ( [id] => 7096392 [patent_doc_number] => 20050128850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Integrated logic circuit and hierarchical design method thereof' [patent_app_type] => utility [patent_app_number] => 11/042061 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2160 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128850.pdf [firstpage_image] =>[orig_patent_app_number] => 11042061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042061
Integrated logic circuit and hierarchical design method thereof Jan 25, 2005 Issued
Array ( [id] => 5621320 [patent_doc_number] => 20060190855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Identifying high E-field structures' [patent_app_type] => utility [patent_app_number] => 11/043721 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3720 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190855.pdf [firstpage_image] =>[orig_patent_app_number] => 11043721 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/043721
Identifying high E-field structures Jan 25, 2005 Issued
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