Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 591142 [patent_doc_number] => 07464361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'System and method for asynchronous logic synthesis from high-level synchronous descriptions' [patent_app_type] => utility [patent_app_number] => 11/040761 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4026 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464361.pdf [firstpage_image] =>[orig_patent_app_number] => 11040761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040761
System and method for asynchronous logic synthesis from high-level synchronous descriptions Jan 20, 2005 Issued
Array ( [id] => 5651121 [patent_doc_number] => 20060136856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Unit-based layout system for passive IC devices' [patent_app_type] => utility [patent_app_number] => 11/039751 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9254 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136856.pdf [firstpage_image] =>[orig_patent_app_number] => 11039751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039751
Unit-based layout system for passive IC devices Jan 18, 2005 Issued
Array ( [id] => 7186139 [patent_doc_number] => 20050125751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method of incorporating interconnect systems into an integrated circuit process flow' [patent_app_type] => utility [patent_app_number] => 11/038744 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12643 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125751.pdf [firstpage_image] =>[orig_patent_app_number] => 11038744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038744
Method of incorporating interconnect systems into an integrated circuit process flow Jan 17, 2005 Issued
Array ( [id] => 645848 [patent_doc_number] => 07124388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Methods to generate state space models by closed forms and transfer functions by recursive algorithms for RC interconnect and transmission line and their model reduction and simulations' [patent_app_type] => utility [patent_app_number] => 11/037701 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 11650 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124388.pdf [firstpage_image] =>[orig_patent_app_number] => 11037701 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037701
Methods to generate state space models by closed forms and transfer functions by recursive algorithms for RC interconnect and transmission line and their model reduction and simulations Jan 17, 2005 Issued
Array ( [id] => 514014 [patent_doc_number] => 07207021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method for estimating a frequency-based ramptime limit' [patent_app_type] => utility [patent_app_number] => 11/036822 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/207/07207021.pdf [firstpage_image] =>[orig_patent_app_number] => 11036822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036822
Method for estimating a frequency-based ramptime limit Jan 13, 2005 Issued
Array ( [id] => 874105 [patent_doc_number] => 07366997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-29 [patent_title] => 'Methods and apparatuses for thermal analysis based circuit design' [patent_app_type] => utility [patent_app_number] => 11/034391 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10869 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366997.pdf [firstpage_image] =>[orig_patent_app_number] => 11034391 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034391
Methods and apparatuses for thermal analysis based circuit design Jan 10, 2005 Issued
Array ( [id] => 912588 [patent_doc_number] => 07334211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'Method for designing a CMOS sensor using parameters' [patent_app_type] => utility [patent_app_number] => 11/029101 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 10233 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/334/07334211.pdf [firstpage_image] =>[orig_patent_app_number] => 11029101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029101
Method for designing a CMOS sensor using parameters Dec 29, 2004 Issued
Array ( [id] => 565084 [patent_doc_number] => 07168053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'Method and system for implementing an analytical wirelength formulation' [patent_app_type] => utility [patent_app_number] => 11/026511 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/168/07168053.pdf [firstpage_image] =>[orig_patent_app_number] => 11026511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026511
Method and system for implementing an analytical wirelength formulation Dec 28, 2004 Issued
Array ( [id] => 201071 [patent_doc_number] => 07640530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method for inspecting mask' [patent_app_type] => utility [patent_app_number] => 11/020281 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 7660 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640530.pdf [firstpage_image] =>[orig_patent_app_number] => 11020281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020281
Method for inspecting mask Dec 26, 2004 Issued
Array ( [id] => 469744 [patent_doc_number] => 07240302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Method and apparatus for relocating elements in a floorplan editor' [patent_app_type] => utility [patent_app_number] => 11/021841 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4650 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240302.pdf [firstpage_image] =>[orig_patent_app_number] => 11021841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021841
Method and apparatus for relocating elements in a floorplan editor Dec 22, 2004 Issued
Array ( [id] => 555743 [patent_doc_number] => 07181706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Selectively reducing the number of cell evaluations in a hardware simulation' [patent_app_type] => utility [patent_app_number] => 11/015491 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6459 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181706.pdf [firstpage_image] =>[orig_patent_app_number] => 11015491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015491
Selectively reducing the number of cell evaluations in a hardware simulation Dec 15, 2004 Issued
Array ( [id] => 526003 [patent_doc_number] => 07197735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Floorplan visualization method using gate count and gate density estimations' [patent_app_type] => utility [patent_app_number] => 11/012741 [patent_app_country] => US [patent_app_date] => 2004-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3695 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197735.pdf [firstpage_image] =>[orig_patent_app_number] => 11012741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012741
Floorplan visualization method using gate count and gate density estimations Dec 14, 2004 Issued
Array ( [id] => 598817 [patent_doc_number] => 07451410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Stackable motherboard and related sensor systems' [patent_app_type] => utility [patent_app_number] => 10/998020 [patent_app_country] => US [patent_app_date] => 2004-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3716 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451410.pdf [firstpage_image] =>[orig_patent_app_number] => 10998020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998020
Stackable motherboard and related sensor systems Nov 25, 2004 Issued
Array ( [id] => 7530123 [patent_doc_number] => 08046729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-25 [patent_title] => 'Method and apparatus for composing and decomposing low-skew networks' [patent_app_type] => utility [patent_app_number] => 10/998101 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5417 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046729.pdf [firstpage_image] =>[orig_patent_app_number] => 10998101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998101
Method and apparatus for composing and decomposing low-skew networks Nov 23, 2004 Issued
Array ( [id] => 582831 [patent_doc_number] => 07472365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Method for computing hold and setup slack without pessimism' [patent_app_type] => utility [patent_app_number] => 10/997621 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9156 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472365.pdf [firstpage_image] =>[orig_patent_app_number] => 10997621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997621
Method for computing hold and setup slack without pessimism Nov 23, 2004 Issued
Array ( [id] => 555105 [patent_doc_number] => 07174532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects' [patent_app_type] => utility [patent_app_number] => 10/992031 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5844 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174532.pdf [firstpage_image] =>[orig_patent_app_number] => 10992031 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992031
Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects Nov 17, 2004 Issued
Array ( [id] => 7107662 [patent_doc_number] => 20050108668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Device and method for floorplanning semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/984861 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4612 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108668.pdf [firstpage_image] =>[orig_patent_app_number] => 10984861 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/984861
Device and method for floorplanning semiconductor integrated circuit Nov 9, 2004 Issued
Array ( [id] => 912582 [patent_doc_number] => 07334208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'Customization of structured ASIC devices using pre-process extraction of routing information' [patent_app_type] => utility [patent_app_number] => 10/904411 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5015 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/334/07334208.pdf [firstpage_image] =>[orig_patent_app_number] => 10904411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904411
Customization of structured ASIC devices using pre-process extraction of routing information Nov 8, 2004 Issued
Array ( [id] => 396977 [patent_doc_number] => 07299440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 10/980171 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3132 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299440.pdf [firstpage_image] =>[orig_patent_app_number] => 10980171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980171
Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium Nov 3, 2004 Issued
Array ( [id] => 7100750 [patent_doc_number] => 20050132322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Mask evaluating method, mask evaluating system, method of manufacturing mask and computer program product' [patent_app_type] => utility [patent_app_number] => 10/976001 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132322.pdf [firstpage_image] =>[orig_patent_app_number] => 10976001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/976001
Mask evaluating method, mask evaluating system, method of manufacturing mask and computer program product Oct 28, 2004 Issued
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