Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5809518 [patent_doc_number] => 20060095874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Power network synthesizer for an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/976411 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6329 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095874.pdf [firstpage_image] =>[orig_patent_app_number] => 10976411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/976411
Power network synthesizer for an integrated circuit design Oct 28, 2004 Issued
Array ( [id] => 5744419 [patent_doc_number] => 20060090145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method of optimizing critical path delay in an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/975981 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2074 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20060090145.pdf [firstpage_image] =>[orig_patent_app_number] => 10975981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975981
Method of optimizing critical path delay in an integrated circuit design Oct 26, 2004 Issued
Array ( [id] => 5744426 [patent_doc_number] => 20060090152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Schematic diagram generation and display system' [patent_app_type] => utility [patent_app_number] => 10/975151 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3925 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20060090152.pdf [firstpage_image] =>[orig_patent_app_number] => 10975151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975151
Schematic diagram generation and display system Oct 26, 2004 Issued
Array ( [id] => 667172 [patent_doc_number] => 07103867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method for manufacturing a power bus on a chip' [patent_app_type] => utility [patent_app_number] => 10/973896 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4477 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103867.pdf [firstpage_image] =>[orig_patent_app_number] => 10973896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973896
Method for manufacturing a power bus on a chip Oct 26, 2004 Issued
Array ( [id] => 447590 [patent_doc_number] => 07257802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method and system for hardware accelerated verification of digital circuit design and its testbench' [patent_app_type] => utility [patent_app_number] => 10/972361 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 8085 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257802.pdf [firstpage_image] =>[orig_patent_app_number] => 10972361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972361
Method and system for hardware accelerated verification of digital circuit design and its testbench Oct 25, 2004 Issued
Array ( [id] => 7603469 [patent_doc_number] => 07117471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Generation of design views having consistent input/output pin definitions' [patent_app_type] => utility [patent_app_number] => 10/971221 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5014 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117471.pdf [firstpage_image] =>[orig_patent_app_number] => 10971221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971221
Generation of design views having consistent input/output pin definitions Oct 21, 2004 Issued
Array ( [id] => 5816679 [patent_doc_number] => 20060085770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'A METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATIC INSERTION AND CORRECTNESS VERIFICATION OF LEVEL SHIFTERS IN INTEGRATED CIRCUITS WITH MULTIPLE VOLTAGE DOMAINS' [patent_app_type] => utility [patent_app_number] => 10/711971 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4544 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085770.pdf [firstpage_image] =>[orig_patent_app_number] => 10711971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711971
Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains Oct 14, 2004 Issued
Array ( [id] => 623493 [patent_doc_number] => 07143373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Method and apparatus for evaluating and debugging assertions' [patent_app_type] => utility [patent_app_number] => 10/965181 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15746 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143373.pdf [firstpage_image] =>[orig_patent_app_number] => 10965181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/965181
Method and apparatus for evaluating and debugging assertions Oct 13, 2004 Issued
Array ( [id] => 486305 [patent_doc_number] => 07225419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Methods for modeling latch transparency' [patent_app_type] => utility [patent_app_number] => 10/962121 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5448 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225419.pdf [firstpage_image] =>[orig_patent_app_number] => 10962121 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962121
Methods for modeling latch transparency Oct 7, 2004 Issued
Array ( [id] => 428010 [patent_doc_number] => 07272812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Semiconductor designing apparatus using sub-circuit recognizer' [patent_app_type] => utility [patent_app_number] => 10/960051 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 14578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272812.pdf [firstpage_image] =>[orig_patent_app_number] => 10960051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960051
Semiconductor designing apparatus using sub-circuit recognizer Oct 7, 2004 Issued
Array ( [id] => 415025 [patent_doc_number] => 07284229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein' [patent_app_type] => utility [patent_app_number] => 10/957261 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9933 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/284/07284229.pdf [firstpage_image] =>[orig_patent_app_number] => 10957261 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957261
Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein Sep 30, 2004 Issued
Array ( [id] => 630044 [patent_doc_number] => 07137086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Assertion checking using two or more cores' [patent_app_type] => utility [patent_app_number] => 10/956854 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4746 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/137/07137086.pdf [firstpage_image] =>[orig_patent_app_number] => 10956854 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956854
Assertion checking using two or more cores Sep 30, 2004 Issued
Array ( [id] => 525846 [patent_doc_number] => 07197722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Optimization of sample plan for overlay' [patent_app_type] => utility [patent_app_number] => 10/956608 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 9277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197722.pdf [firstpage_image] =>[orig_patent_app_number] => 10956608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956608
Optimization of sample plan for overlay Sep 29, 2004 Issued
Array ( [id] => 536071 [patent_doc_number] => 07194707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method and apparatus for depopulating peripheral input/output cells' [patent_app_type] => utility [patent_app_number] => 10/711431 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6893 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194707.pdf [firstpage_image] =>[orig_patent_app_number] => 10711431 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711431
Method and apparatus for depopulating peripheral input/output cells Sep 16, 2004 Issued
Array ( [id] => 7161024 [patent_doc_number] => 20050028135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Interactive loop configuration in a behavioral synthesis tool' [patent_app_type] => utility [patent_app_number] => 10/930235 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4410 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20050028135.pdf [firstpage_image] =>[orig_patent_app_number] => 10930235 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930235
Interactive loop configuration in a behavioral synthesis tool Aug 29, 2004 Issued
Array ( [id] => 623525 [patent_doc_number] => 07143389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Systems and methods for generating node level bypass capacitor models' [patent_app_type] => utility [patent_app_number] => 11/089581 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3811 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143389.pdf [firstpage_image] =>[orig_patent_app_number] => 11089581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089581
Systems and methods for generating node level bypass capacitor models Jul 27, 2004 Issued
Array ( [id] => 816701 [patent_doc_number] => 07415691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method and system for outputting a sequence of commands and data described by a flowchart' [patent_app_type] => utility [patent_app_number] => 10/894781 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415691.pdf [firstpage_image] =>[orig_patent_app_number] => 10894781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894781
Method and system for outputting a sequence of commands and data described by a flowchart Jul 19, 2004 Issued
Array ( [id] => 5790940 [patent_doc_number] => 20060012006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Capacitors integrated with inductive components' [patent_app_type] => utility [patent_app_number] => 10/894521 [patent_app_country] => US [patent_app_date] => 2004-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4131 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20060012006.pdf [firstpage_image] =>[orig_patent_app_number] => 10894521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894521
Capacitors integrated with inductive components Jul 18, 2004 Issued
Array ( [id] => 6979780 [patent_doc_number] => 20050289498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Processing and verifying retimed sequential elements in a circuit design' [patent_app_type] => utility [patent_app_number] => 10/879781 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2905 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289498.pdf [firstpage_image] =>[orig_patent_app_number] => 10879781 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/879781
Processing and verifying retimed sequential elements in a circuit design Jun 27, 2004 Issued
Array ( [id] => 616003 [patent_doc_number] => 07149995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Graphical interface to layout processing components and connections' [patent_app_type] => utility [patent_app_number] => 10/877271 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3830 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149995.pdf [firstpage_image] =>[orig_patent_app_number] => 10877271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877271
Graphical interface to layout processing components and connections Jun 24, 2004 Issued
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