Jeffrey T. Knapp

Array ( [id] => 623485 [patent_doc_number] => 07143368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'DSP design system level power estimation' [patent_app_type] => utility [patent_app_number] => 10/866391 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6614 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143368.pdf [firstpage_image] =>[orig_patent_app_number] => 10866391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7057502 [patent_doc_number] => 20050278677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Novel test structure for automatic dynamic negative-bias temperature instability testing' [patent_app_type] => utility [patent_app_number] => 10/864951 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3885 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278677.pdf [firstpage_image] =>[orig_patent_app_number] => 10864951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 486300 [patent_doc_number] => 07225418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same' [patent_app_type] => utility [patent_app_number] => 10/863231 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 73 [patent_no_of_words] => 15698 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225418.pdf [firstpage_image] =>[orig_patent_app_number] => 10863231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 882709 [patent_doc_number] => 07360196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Technology mapping for programming and design of a programmable logic device by equating logic expressions' [patent_app_type] => utility [patent_app_number] => 10/859842 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360196.pdf [firstpage_image] =>[orig_patent_app_number] => 10859842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 882678 [patent_doc_number] => 07360189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method and apparatus for enabling waveform display in a system design model' [patent_app_type] => utility [patent_app_number] => 10/858301 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360189.pdf [firstpage_image] =>[orig_patent_app_number] => 10858301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 898642 [patent_doc_number] => 07346878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'Apparatus and methods for providing in-chip microtargets for metrology or inspection' [patent_app_type] => utility [patent_app_number] => 10/858836 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9077 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346878.pdf [firstpage_image] =>[orig_patent_app_number] => 10858836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7621075 [patent_doc_number] => 06978427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Literal sharing method for fast sum-of-products logic' [patent_app_type] => utility [patent_app_number] => 10/847965 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7835 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978427.pdf [firstpage_image] =>[orig_patent_app_number] => 10847965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 630042 [patent_doc_number] => 07137084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-14 [patent_title] => 'Similarity-driven synthesis for equivalence checking of complex designs' [patent_app_type] => utility [patent_app_number] => 10/832771 [patent_app_country] => US [patent_app_date] => 2004-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/137/07137084.pdf [firstpage_image] =>[orig_patent_app_number] => 10832771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 726622 [patent_doc_number] => 07051296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Method and apparatus for parallel carry chains' [patent_app_type] => utility [patent_app_number] => 10/817586 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5522 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051296.pdf [firstpage_image] =>[orig_patent_app_number] => 10817586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 898521 [patent_doc_number] => 07346860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'User non-volatile memory interface megafunction' [patent_app_type] => utility [patent_app_number] => 10/796699 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3302 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346860.pdf [firstpage_image] =>[orig_patent_app_number] => 10796699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7441436 [patent_doc_number] => 20040163064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Line width check in layout database' [patent_app_type] => new [patent_app_number] => 10/782701 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3446 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20040163064.pdf [firstpage_image] =>[orig_patent_app_number] => 10782701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 418401 [patent_doc_number] => 07281228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Configurable memory system for embedded processors' [patent_app_type] => utility [patent_app_number] => 10/777863 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3519 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281228.pdf [firstpage_image] =>[orig_patent_app_number] => 10777863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 481795 [patent_doc_number] => 07228520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method and apparatus for a programmable interface of a soft platform on a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/769331 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 12625 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228520.pdf [firstpage_image] =>[orig_patent_app_number] => 10769331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 702598 [patent_doc_number] => 07073142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Wiring diagram verifying method, program, and apparatus' [patent_app_type] => utility [patent_app_number] => 10/752701 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 8775 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/073/07073142.pdf [firstpage_image] =>[orig_patent_app_number] => 10752701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 691275 [patent_doc_number] => 07080337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Non-uniform decoupling capacitor distribution for providing more uniform noise reduction across chip' [patent_app_type] => utility [patent_app_number] => 10/749501 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6093 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080337.pdf [firstpage_image] =>[orig_patent_app_number] => 10749501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 637675 [patent_doc_number] => 07131081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Scalable scan-path test point insertion technique' [patent_app_type] => utility [patent_app_number] => 10/736879 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12901 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/131/07131081.pdf [firstpage_image] =>[orig_patent_app_number] => 10736879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 663329 [patent_doc_number] => 07107562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Method and apparatus for the arrangement of contact-making elements of components of an integrated circuit, computer-readable storage medium and program element' [patent_app_type] => utility [patent_app_number] => 10/719005 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6587 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107562.pdf [firstpage_image] =>[orig_patent_app_number] => 10719005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7107666 [patent_doc_number] => 20050108672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method of generating a physical netlist for a hierarchical integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/718291 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4124 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108672.pdf [firstpage_image] =>[orig_patent_app_number] => 10718291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 685607 [patent_doc_number] => 07082594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-25 [patent_title] => 'Compilation in a high-level modeling system' [patent_app_type] => utility [patent_app_number] => 10/717041 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4179 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082594.pdf [firstpage_image] =>[orig_patent_app_number] => 10717041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 758143 [patent_doc_number] => 07024652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'System and method for adaptive partitioning of circuit components during simulation' [patent_app_type] => utility [patent_app_number] => 10/713751 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024652.pdf [firstpage_image] =>[orig_patent_app_number] => 10713751 [rel_patent_id] =>[rel_patent_doc_number] =>)