Jeffrey T. Knapp

Array ( [id] => 7477229 [patent_doc_number] => 20040098679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Circuit design method, apparatus, and program' [patent_app_type] => new [patent_app_number] => 10/706811 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4972 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098679.pdf [firstpage_image] =>[orig_patent_app_number] => 10706811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 600482 [patent_doc_number] => 07437692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Memory debugger for system-on-a-chip designs' [patent_app_type] => utility [patent_app_number] => 10/705101 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9683 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437692.pdf [firstpage_image] =>[orig_patent_app_number] => 10705101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 933613 [patent_doc_number] => 06981237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Command user interface with programmable decoder' [patent_app_type] => utility [patent_app_number] => 10/703322 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4225 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981237.pdf [firstpage_image] =>[orig_patent_app_number] => 10703322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6920245 [patent_doc_number] => 20050097497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method of designing custom circuit device' [patent_app_type] => utility [patent_app_number] => 10/699241 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10615 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097497.pdf [firstpage_image] =>[orig_patent_app_number] => 10699241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 633590 [patent_doc_number] => 07134110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Methods and apparatus for improving critical path analysis using gate delay' [patent_app_type] => utility [patent_app_number] => 10/697603 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3502 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134110.pdf [firstpage_image] =>[orig_patent_app_number] => 10697603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 536281 [patent_doc_number] => 07194723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Techniques for mapping functions to lookup tables on programmable circuits' [patent_app_type] => utility [patent_app_number] => 10/694919 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4087 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194723.pdf [firstpage_image] =>[orig_patent_app_number] => 10694919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 680496 [patent_doc_number] => 07089525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/688975 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 10666 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089525.pdf [firstpage_image] =>[orig_patent_app_number] => 10688975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 671750 [patent_doc_number] => 07096447 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout' [patent_app_type] => utility [patent_app_number] => 10/686471 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 7224 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096447.pdf [firstpage_image] =>[orig_patent_app_number] => 10686471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7225924 [patent_doc_number] => 20050078544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Efficient implementation of multiple clock domain accesses to diffused memories in structured ASICs' [patent_app_type] => utility [patent_app_number] => 10/684733 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3543 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20050078544.pdf [firstpage_image] =>[orig_patent_app_number] => 10684733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7246751 [patent_doc_number] => 20050081173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'IC design planning method and system' [patent_app_type] => utility [patent_app_number] => 10/685211 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9694 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20050081173.pdf [firstpage_image] =>[orig_patent_app_number] => 10685211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7603470 [patent_doc_number] => 07117470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/684211 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 5322 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117470.pdf [firstpage_image] =>[orig_patent_app_number] => 10684211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 671729 [patent_doc_number] => 07096437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Method and apparatus for a chaotic computing module using threshold reference signal implementation' [patent_app_type] => utility [patent_app_number] => 10/680271 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3581 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096437.pdf [firstpage_image] =>[orig_patent_app_number] => 10680271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 794453 [patent_doc_number] => 06983429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Formal proof methods for analyzing circuit loading problems under operating conditions' [patent_app_type] => utility [patent_app_number] => 10/675851 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2449 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983429.pdf [firstpage_image] =>[orig_patent_app_number] => 10675851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7160862 [patent_doc_number] => 20040075470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/671474 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5619 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20040075470.pdf [firstpage_image] =>[orig_patent_app_number] => 10671474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7220536 [patent_doc_number] => 20050077602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Functionality based package design' [patent_app_type] => utility [patent_app_number] => 10/673721 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077602.pdf [firstpage_image] =>[orig_patent_app_number] => 10673721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 933611 [patent_doc_number] => 06981236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method for modeling semiconductor device and network' [patent_app_type] => utility [patent_app_number] => 10/668261 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3723 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981236.pdf [firstpage_image] =>[orig_patent_app_number] => 10668261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7271498 [patent_doc_number] => 20040060016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Time synthesis for power optimization of high performance circuits' [patent_app_type] => new [patent_app_number] => 10/665521 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3951 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20040060016.pdf [firstpage_image] =>[orig_patent_app_number] => 10665521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5663214 [patent_doc_number] => 20060253810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Integrated circuit design to optimize manufacturability' [patent_app_type] => utility [patent_app_number] => 10/572151 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3510 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253810.pdf [firstpage_image] =>[orig_patent_app_number] => 10572151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 745490 [patent_doc_number] => 07036096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Estimating capacitances using information including feature sizes extracted from a netlist' [patent_app_type] => utility [patent_app_number] => 10/657431 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4432 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/036/07036096.pdf [firstpage_image] =>[orig_patent_app_number] => 10657431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 435229 [patent_doc_number] => 07266790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method and system for logic equivalence checking' [patent_app_type] => utility [patent_app_number] => 10/656801 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4198 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266790.pdf [firstpage_image] =>[orig_patent_app_number] => 10656801 [rel_patent_id] =>[rel_patent_doc_number] =>)