Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 717225 [patent_doc_number] => 07058912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Notifying status of execution of jobs used to characterize cells in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/651981 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3691 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/058/07058912.pdf [firstpage_image] =>[orig_patent_app_number] => 10651981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651981
Notifying status of execution of jobs used to characterize cells in an integrated circuit Sep 1, 2003 Issued
Array ( [id] => 659712 [patent_doc_number] => 07111275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Electronic circuit design analysis system' [patent_app_type] => utility [patent_app_number] => 10/651151 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7119 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111275.pdf [firstpage_image] =>[orig_patent_app_number] => 10651151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651151
Electronic circuit design analysis system Aug 27, 2003 Issued
Array ( [id] => 794486 [patent_doc_number] => 06983442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith' [patent_app_type] => utility [patent_app_number] => 10/649401 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7246 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983442.pdf [firstpage_image] =>[orig_patent_app_number] => 10649401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649401
Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith Aug 25, 2003 Issued
Array ( [id] => 7293624 [patent_doc_number] => 20040111684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Design method of logic circuit' [patent_app_type] => new [patent_app_number] => 10/642761 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10664 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111684.pdf [firstpage_image] =>[orig_patent_app_number] => 10642761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642761
Design method of logic circuit using data flow graph Aug 18, 2003 Issued
Array ( [id] => 929685 [patent_doc_number] => 07315998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Integrated circuit arrangement with intermediate materials and associated components' [patent_app_type] => utility [patent_app_number] => 10/526881 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6237 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315998.pdf [firstpage_image] =>[orig_patent_app_number] => 10526881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/526881
Integrated circuit arrangement with intermediate materials and associated components Aug 13, 2003 Issued
Array ( [id] => 726703 [patent_doc_number] => 07051313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Automatic generation of programmable logic device architectures' [patent_app_type] => utility [patent_app_number] => 10/641193 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7329 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051313.pdf [firstpage_image] =>[orig_patent_app_number] => 10641193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641193
Automatic generation of programmable logic device architectures Aug 12, 2003 Issued
Array ( [id] => 736517 [patent_doc_number] => 07043713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Implementing programmable logic array embedded in mask-programmed ASIC' [patent_app_type] => utility [patent_app_number] => 10/640171 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7310 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/043/07043713.pdf [firstpage_image] =>[orig_patent_app_number] => 10640171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640171
Implementing programmable logic array embedded in mask-programmed ASIC Aug 11, 2003 Issued
Array ( [id] => 7339790 [patent_doc_number] => 20040133412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Method for predicting performance of integrated circuit and method for designing the circuit' [patent_app_type] => new [patent_app_number] => 10/627641 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2767 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133412.pdf [firstpage_image] =>[orig_patent_app_number] => 10627641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627641
Method for predicting performance of integrated circuit and method for designing the circuit Jul 27, 2003 Issued
Array ( [id] => 7673840 [patent_doc_number] => 20040128278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Printed wiring board design aiding system, printed wiring board CAD system, and record medium' [patent_app_type] => new [patent_app_number] => 10/624491 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5591 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128278.pdf [firstpage_image] =>[orig_patent_app_number] => 10624491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624491
Printed wiring board design aiding system, printed wiring board CAD system, and record medium Jul 22, 2003 Issued
Array ( [id] => 7368292 [patent_doc_number] => 20040015804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise' [patent_app_type] => new [patent_app_number] => 10/620535 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 28794 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015804.pdf [firstpage_image] =>[orig_patent_app_number] => 10620535 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620535
Computer aided design apparatus for aiding design of a printed wiring board to effectively reduce noise Jul 15, 2003 Issued
Array ( [id] => 5249042 [patent_doc_number] => 20070245276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'System, method and computer program product for designing connecting terminals of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/617931 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7995 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245276.pdf [firstpage_image] =>[orig_patent_app_number] => 10617931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617931
System, method and computer program product for designing connecting terminals of semiconductor device Jul 10, 2003 Issued
Array ( [id] => 7092097 [patent_doc_number] => 20050010885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Pulse-width limited chip clock design' [patent_app_type] => utility [patent_app_number] => 10/616881 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3533 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010885.pdf [firstpage_image] =>[orig_patent_app_number] => 10616881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/616881
Pulse-width limited chip clock design Jul 9, 2003 Issued
Array ( [id] => 7373035 [patent_doc_number] => 20040006754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Semiconductor integrated circuit device and layout method of patterns for semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/609572 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6949 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20040006754.pdf [firstpage_image] =>[orig_patent_app_number] => 10609572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609572
Semiconductor integrated circuit device and layout method of patterns for semiconductor integrated circuit device Jun 30, 2003 Issued
Array ( [id] => 792890 [patent_doc_number] => 06986119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Method of forming tree structure type circuit, and computer product' [patent_app_type] => utility [patent_app_number] => 10/460161 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3791 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986119.pdf [firstpage_image] =>[orig_patent_app_number] => 10460161 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460161
Method of forming tree structure type circuit, and computer product Jun 12, 2003 Issued
Array ( [id] => 7333775 [patent_doc_number] => 20040255258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout' [patent_app_type] => new [patent_app_number] => 10/461041 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7642 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255258.pdf [firstpage_image] =>[orig_patent_app_number] => 10461041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461041
Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout Jun 12, 2003 Issued
Array ( [id] => 7234229 [patent_doc_number] => 20050262466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Method for modifying design data for the production of a component and corresponding units' [patent_app_type] => utility [patent_app_number] => 10/518291 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5886 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262466.pdf [firstpage_image] =>[orig_patent_app_number] => 10518291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/518291
Method for modifying design data for the production of a component and corresponding units Jun 4, 2003 Issued
Array ( [id] => 6679730 [patent_doc_number] => 20030229871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Method of generating timing constraint model of logic circuit, program for generating timing constraint model of logic circuit, and timing-driven layout method of using the timing constraint model' [patent_app_type] => new [patent_app_number] => 10/453621 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7855 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20030229871.pdf [firstpage_image] =>[orig_patent_app_number] => 10453621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453621
Method of generating timing constraint model of logic circuit, program for generating timing constraint model of logic circuit, and timing-driven layout method of using the timing constraint model Jun 3, 2003 Abandoned
Array ( [id] => 561388 [patent_doc_number] => 07178124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-13 [patent_title] => 'Methods, algorithms, software, architectures and system for placing clocked components and routing timing signals in a circuit and/or layout' [patent_app_type] => utility [patent_app_number] => 10/452811 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14272 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/178/07178124.pdf [firstpage_image] =>[orig_patent_app_number] => 10452811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452811
Methods, algorithms, software, architectures and system for placing clocked components and routing timing signals in a circuit and/or layout May 29, 2003 Issued
Array ( [id] => 965757 [patent_doc_number] => 06950996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Interconnect delay and slew metrics based on the lognormal distribution' [patent_app_type] => utility [patent_app_number] => 10/448241 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6081 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950996.pdf [firstpage_image] =>[orig_patent_app_number] => 10448241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448241
Interconnect delay and slew metrics based on the lognormal distribution May 28, 2003 Issued
Array ( [id] => 7321803 [patent_doc_number] => 20040225989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Representation of wiring in a design layout' [patent_app_type] => new [patent_app_number] => 10/443811 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9214 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225989.pdf [firstpage_image] =>[orig_patent_app_number] => 10443811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443811
Plane representation of wiring in a design layout May 20, 2003 Issued
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