Jeffrey T. Knapp

Array ( [id] => 7271514 [patent_doc_number] => 20040060032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Automated system for designing and developing field programmable gate arrays' [patent_app_type] => new [patent_app_number] => 10/441581 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20040060032.pdf [firstpage_image] =>[orig_patent_app_number] => 10441581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771688 [patent_doc_number] => 07010763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method of optimizing and analyzing selected portions of a digital integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/436213 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8283 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010763.pdf [firstpage_image] =>[orig_patent_app_number] => 10436213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7321726 [patent_doc_number] => 20040225970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Method and apparatus for circuit design and retiming' [patent_app_type] => new [patent_app_number] => 10/435061 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11013 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225970.pdf [firstpage_image] =>[orig_patent_app_number] => 10435061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 645855 [patent_doc_number] => 07124391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method and apparatus for dynamically connecting modules in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/427231 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124391.pdf [firstpage_image] =>[orig_patent_app_number] => 10427231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7292377 [patent_doc_number] => 20040212393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Reconfigurable fabric for SoCs' [patent_app_type] => new [patent_app_number] => 10/425101 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5395 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212393.pdf [firstpage_image] =>[orig_patent_app_number] => 10425101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 965759 [patent_doc_number] => 06950998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Place-and-route with power analysis' [patent_app_type] => utility [patent_app_number] => 10/421251 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3442 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950998.pdf [firstpage_image] =>[orig_patent_app_number] => 10421251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 981846 [patent_doc_number] => 06931617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Mask cost driven logic optimization and synthesis' [patent_app_type] => utility [patent_app_number] => 10/420951 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4057 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931617.pdf [firstpage_image] =>[orig_patent_app_number] => 10420951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 561237 [patent_doc_number] => 07178112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-13 [patent_title] => 'Management of functions for block diagrams' [patent_app_type] => utility [patent_app_number] => 10/418002 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 49 [patent_no_of_words] => 22342 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/178/07178112.pdf [firstpage_image] =>[orig_patent_app_number] => 10418002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 498775 [patent_doc_number] => 07216330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices by registering a user specified procedure' [patent_app_type] => utility [patent_app_number] => 10/413081 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4857 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216330.pdf [firstpage_image] =>[orig_patent_app_number] => 10413081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7473270 [patent_doc_number] => 20040199893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same' [patent_app_type] => new [patent_app_number] => 10/403501 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3213 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20040199893.pdf [firstpage_image] =>[orig_patent_app_number] => 10403501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 766175 [patent_doc_number] => 07013443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon' [patent_app_type] => utility [patent_app_number] => 10/393921 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4872 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/013/07013443.pdf [firstpage_image] =>[orig_patent_app_number] => 10393921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 774480 [patent_doc_number] => 07007261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-28 [patent_title] => 'Translation of an electronic integrated circuit design into hardware description language using circuit description template' [patent_app_type] => utility [patent_app_number] => 10/388711 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007261.pdf [firstpage_image] =>[orig_patent_app_number] => 10388711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7611270 [patent_doc_number] => 06904572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Method, apparatus and program for designing a semiconductor integrated circuit by adjusting loading of paths' [patent_app_type] => utility [patent_app_number] => 10/378731 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 7953 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904572.pdf [firstpage_image] =>[orig_patent_app_number] => 10378731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6857835 [patent_doc_number] => 20030131336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Programmable element latch circuit' [patent_app_type] => new [patent_app_number] => 10/372196 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3504 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131336.pdf [firstpage_image] =>[orig_patent_app_number] => 10372196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 984844 [patent_doc_number] => 06928631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Circuit design method and computer program product' [patent_app_type] => utility [patent_app_number] => 10/366411 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3914 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928631.pdf [firstpage_image] =>[orig_patent_app_number] => 10366411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7441443 [patent_doc_number] => 20040163065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'A METHOD OF BYPASSING A PLURALITY OF CLOCK TREES IN EDA TOOLS' [patent_app_type] => new [patent_app_number] => 10/248751 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2013 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20040163065.pdf [firstpage_image] =>[orig_patent_app_number] => 10248751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1071066 [patent_doc_number] => 06845492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Signal via impedance adjustment tool' [patent_app_type] => utility [patent_app_number] => 10/365831 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 41 [patent_no_of_words] => 21306 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845492.pdf [firstpage_image] =>[orig_patent_app_number] => 10365831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7247434 [patent_doc_number] => 20040158807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'METHOD FOR SYNTHESIZING DOMINO LOGIC CIRCUITS' [patent_app_type] => new [patent_app_number] => 10/248721 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5149 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158807.pdf [firstpage_image] =>[orig_patent_app_number] => 10248721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 633583 [patent_doc_number] => 07134109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Parameter oriented graphical representation of hardware timing and triggering capabilities with contextual information' [patent_app_type] => utility [patent_app_number] => 10/361661 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 16315 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134109.pdf [firstpage_image] =>[orig_patent_app_number] => 10361661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 713953 [patent_doc_number] => 07062741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Wire bond padring bond pad checker program' [patent_app_type] => utility [patent_app_number] => 10/351101 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5544 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062741.pdf [firstpage_image] =>[orig_patent_app_number] => 10351101 [rel_patent_id] =>[rel_patent_doc_number] =>)