Jeffrey T. Knapp

Array ( [id] => 6698260 [patent_doc_number] => 20030110454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Active impedance compensation' [patent_app_type] => new [patent_app_number] => 10/346859 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4441 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110454.pdf [firstpage_image] =>[orig_patent_app_number] => 10346859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6661193 [patent_doc_number] => 20030135837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method and apparatus for automatic arrangement and wiring for a semiconductor integrated circuit design and wiring program therefor' [patent_app_type] => new [patent_app_number] => 10/346801 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135837.pdf [firstpage_image] =>[orig_patent_app_number] => 10346801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 774483 [patent_doc_number] => 07007263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Design flow method for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/342281 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2828 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007263.pdf [firstpage_image] =>[orig_patent_app_number] => 10342281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 937748 [patent_doc_number] => 06976234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Apparatus and method for measuring characteristics of dynamic electrical signals in integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/341721 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4539 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976234.pdf [firstpage_image] =>[orig_patent_app_number] => 10341721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7613761 [patent_doc_number] => 06898770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Split and merge design flow concept for fast turnaround time of circuit layout design' [patent_app_type] => utility [patent_app_number] => 10/339821 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2932 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898770.pdf [firstpage_image] =>[orig_patent_app_number] => 10339821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6857832 [patent_doc_number] => 20030131333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout' [patent_app_type] => new [patent_app_number] => 10/338311 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6839 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131333.pdf [firstpage_image] =>[orig_patent_app_number] => 10338311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 702609 [patent_doc_number] => 07073145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Programmable delay method for hierarchical signal balancing' [patent_app_type] => utility [patent_app_number] => 10/248301 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2188 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/073/07073145.pdf [firstpage_image] =>[orig_patent_app_number] => 10248301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6857822 [patent_doc_number] => 20030131323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Method of schematic-level AMS topology optimization using direct representations' [patent_app_type] => new [patent_app_number] => 10/337271 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131323.pdf [firstpage_image] =>[orig_patent_app_number] => 10337271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771704 [patent_doc_number] => 07010771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Method and apparatus for searching for a global path' [patent_app_type] => utility [patent_app_number] => 10/335251 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 16531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010771.pdf [firstpage_image] =>[orig_patent_app_number] => 10335251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673486 [patent_doc_number] => 20040128632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Netlist redundancy detection and global simplification' [patent_app_type] => new [patent_app_number] => 10/334731 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128632.pdf [firstpage_image] =>[orig_patent_app_number] => 10334731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673481 [patent_doc_number] => 20040128637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Apparatus and method for visualizing and analyzing resistance networks' [patent_app_type] => new [patent_app_number] => 10/331521 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4911 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128637.pdf [firstpage_image] =>[orig_patent_app_number] => 10331521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6704320 [patent_doc_number] => 20030151054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method for automatically defining a part model' [patent_app_type] => new [patent_app_number] => 10/330891 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11417 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151054.pdf [firstpage_image] =>[orig_patent_app_number] => 10330891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7309616 [patent_doc_number] => 20040117748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method for creating derivative integrated circuit layouts for related products' [patent_app_type] => new [patent_app_number] => 10/318639 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117748.pdf [firstpage_image] =>[orig_patent_app_number] => 10318639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 667175 [patent_doc_number] => 07103869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Method of verifying IC mask sets' [patent_app_type] => utility [patent_app_number] => 10/317147 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4540 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103869.pdf [firstpage_image] =>[orig_patent_app_number] => 10317147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 947841 [patent_doc_number] => 06966044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources' [patent_app_type] => utility [patent_app_number] => 10/316101 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/966/06966044.pdf [firstpage_image] =>[orig_patent_app_number] => 10316101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 984835 [patent_doc_number] => 06928626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'System and method for modeling of circuit components' [patent_app_type] => utility [patent_app_number] => 10/313061 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928626.pdf [firstpage_image] =>[orig_patent_app_number] => 10313061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 659710 [patent_doc_number] => 07111274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations' [patent_app_type] => utility [patent_app_number] => 10/310260 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 7021 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111274.pdf [firstpage_image] =>[orig_patent_app_number] => 10310260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6703249 [patent_doc_number] => 20030226129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Interactive floor planner apparatus' [patent_app_type] => new [patent_app_number] => 10/307871 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6402 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20030226129.pdf [firstpage_image] =>[orig_patent_app_number] => 10307871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7138951 [patent_doc_number] => 20040045015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Common interface framework for developing field programmable device based applications independent of target circuit board' [patent_app_type] => new [patent_app_number] => 10/303441 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7992 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20040045015.pdf [firstpage_image] =>[orig_patent_app_number] => 10303441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1030730 [patent_doc_number] => 06883147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method and system for generating a circuit design including a peripheral component connected to a bus' [patent_app_type] => utility [patent_app_number] => 10/304471 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 6806 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883147.pdf [firstpage_image] =>[orig_patent_app_number] => 10304471 [rel_patent_id] =>[rel_patent_doc_number] =>)