
Jeffrey T. Knapp
Examiner (ID: 7182)
| Most Active Art Unit | 3205 |
| Art Unit(s) | 1722, 3616, 3202, 1725, 3205 |
| Total Applications | 712 |
| Issued Applications | 662 |
| Pending Applications | 22 |
| Abandoned Applications | 28 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7626792
[patent_doc_number] => 06807653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-19
[patent_title] => 'Recovery path designing circuit, method and program thereof'
[patent_app_type] => B2
[patent_app_number] => 10/298315
[patent_app_country] => US
[patent_app_date] => 2002-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 6243
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/807/06807653.pdf
[firstpage_image] =>[orig_patent_app_number] => 10298315
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/298315 | Recovery path designing circuit, method and program thereof | Nov 14, 2002 | Issued |
Array
(
[id] => 7216072
[patent_doc_number] => 20040088668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Virtual path'
[patent_app_type] => new
[patent_app_number] => 10/285301
[patent_app_country] => US
[patent_app_date] => 2002-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4759
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20040088668.pdf
[firstpage_image] =>[orig_patent_app_number] => 10285301
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/285301 | Virtual path for interconnect fabric using bandwidth process | Oct 30, 2002 | Issued |
Array
(
[id] => 1025106
[patent_doc_number] => 06889368
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-03
[patent_title] => 'Method and apparatus for localizing faults within a programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 10/280611
[patent_app_country] => US
[patent_app_date] => 2002-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4479
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/889/06889368.pdf
[firstpage_image] =>[orig_patent_app_number] => 10280611
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/280611 | Method and apparatus for localizing faults within a programmable logic device | Oct 24, 2002 | Issued |
Array
(
[id] => 6659892
[patent_doc_number] => 20030079194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-24
[patent_title] => 'Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program'
[patent_app_type] => new
[patent_app_number] => 10/279403
[patent_app_country] => US
[patent_app_date] => 2002-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 13394
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20030079194.pdf
[firstpage_image] =>[orig_patent_app_number] => 10279403
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279403 | Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program | Oct 23, 2002 | Issued |
Array
(
[id] => 933615
[patent_doc_number] => 06981238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Verification of integrated circuit designs using buffer control'
[patent_app_type] => utility
[patent_app_number] => 10/277541
[patent_app_country] => US
[patent_app_date] => 2002-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4109
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/981/06981238.pdf
[firstpage_image] =>[orig_patent_app_number] => 10277541
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/277541 | Verification of integrated circuit designs using buffer control | Oct 21, 2002 | Issued |
Array
(
[id] => 1001854
[patent_doc_number] => 06912699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-28
[patent_title] => 'Testing design for flip chip connection process'
[patent_app_type] => utility
[patent_app_number] => 10/274181
[patent_app_country] => US
[patent_app_date] => 2002-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1756
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/912/06912699.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274181 | Testing design for flip chip connection process | Oct 17, 2002 | Issued |
Array
(
[id] => 745744
[patent_doc_number] => 07036109
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-04-25
[patent_title] => 'Imaging integrated circuits with focused ion beam'
[patent_app_type] => utility
[patent_app_number] => 10/274431
[patent_app_country] => US
[patent_app_date] => 2002-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5408
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/036/07036109.pdf
[firstpage_image] =>[orig_patent_app_number] => 10274431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/274431 | Imaging integrated circuits with focused ion beam | Oct 16, 2002 | Issued |
Array
(
[id] => 947839
[patent_doc_number] => 06966043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-15
[patent_title] => 'Method for designing minimal cost, timing correct hardware during circuit synthesis'
[patent_app_type] => utility
[patent_app_number] => 10/266831
[patent_app_country] => US
[patent_app_date] => 2002-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4228
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/966/06966043.pdf
[firstpage_image] =>[orig_patent_app_number] => 10266831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/266831 | Method for designing minimal cost, timing correct hardware during circuit synthesis | Oct 6, 2002 | Issued |
Array
(
[id] => 7603471
[patent_doc_number] => 07117469
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-03
[patent_title] => 'Method of optimizing placement and routing of edge logic in padring layout design'
[patent_app_type] => utility
[patent_app_number] => 10/264691
[patent_app_country] => US
[patent_app_date] => 2002-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 42
[patent_no_of_words] => 11629
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/117/07117469.pdf
[firstpage_image] =>[orig_patent_app_number] => 10264691
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/264691 | Method of optimizing placement and routing of edge logic in padring layout design | Oct 2, 2002 | Issued |
Array
(
[id] => 1062324
[patent_doc_number] => 06854094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Method and apparatus for laying out power supply wiring'
[patent_app_type] => utility
[patent_app_number] => 10/261491
[patent_app_country] => US
[patent_app_date] => 2002-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/854/06854094.pdf
[firstpage_image] =>[orig_patent_app_number] => 10261491
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/261491 | Method and apparatus for laying out power supply wiring | Oct 1, 2002 | Issued |
Array
(
[id] => 7282422
[patent_doc_number] => 20040064799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'System and method for correlated clock networks'
[patent_app_type] => new
[patent_app_number] => 10/260251
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4133
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20040064799.pdf
[firstpage_image] =>[orig_patent_app_number] => 10260251
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/260251 | System and method for correlated clock networks | Sep 29, 2002 | Issued |
Array
(
[id] => 7282418
[patent_doc_number] => 20040064795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Via enclosure rule check in a multi-wide object class design layout'
[patent_app_type] => new
[patent_app_number] => 10/260811
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 17127
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20040064795.pdf
[firstpage_image] =>[orig_patent_app_number] => 10260811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/260811 | Via enclosure rule check in a multi-wide object class design layout | Sep 29, 2002 | Issued |
Array
(
[id] => 1052703
[patent_doc_number] => 06862724
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-01
[patent_title] => 'Reconfigurable programmable logic system with peripheral identification data'
[patent_app_type] => utility
[patent_app_number] => 10/260111
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4949
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/862/06862724.pdf
[firstpage_image] =>[orig_patent_app_number] => 10260111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/260111 | Reconfigurable programmable logic system with peripheral identification data | Sep 24, 2002 | Issued |
Array
(
[id] => 7962105
[patent_doc_number] => 06681377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-20
[patent_title] => 'Timing resynthesis in a multi-clock emulation system'
[patent_app_type] => B2
[patent_app_number] => 10/246788
[patent_app_country] => US
[patent_app_date] => 2002-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 11435
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/681/06681377.pdf
[firstpage_image] =>[orig_patent_app_number] => 10246788
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/246788 | Timing resynthesis in a multi-clock emulation system | Sep 16, 2002 | Issued |
Array
(
[id] => 7621069
[patent_doc_number] => 06978433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-20
[patent_title] => 'Method and apparatus for placement of vias'
[patent_app_type] => utility
[patent_app_number] => 10/245162
[patent_app_country] => US
[patent_app_date] => 2002-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4329
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/978/06978433.pdf
[firstpage_image] =>[orig_patent_app_number] => 10245162
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/245162 | Method and apparatus for placement of vias | Sep 15, 2002 | Issued |
Array
(
[id] => 1186082
[patent_doc_number] => 06745380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-01
[patent_title] => 'Method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor production, and computer program therefor'
[patent_app_type] => B2
[patent_app_number] => 10/233691
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4171
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/745/06745380.pdf
[firstpage_image] =>[orig_patent_app_number] => 10233691
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233691 | Method for optimizing and method for producing a layout for a mask, preferably for use in semiconductor production, and computer program therefor | Sep 2, 2002 | Issued |
Array
(
[id] => 7611271
[patent_doc_number] => 06904571
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-07
[patent_title] => 'Algorithm and methodology for the polygonalization of sparse circuit schematics'
[patent_app_type] => utility
[patent_app_number] => 10/234411
[patent_app_country] => US
[patent_app_date] => 2002-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 10898
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/904/06904571.pdf
[firstpage_image] =>[orig_patent_app_number] => 10234411
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/234411 | Algorithm and methodology for the polygonalization of sparse circuit schematics | Sep 2, 2002 | Issued |
Array
(
[id] => 641372
[patent_doc_number] => 07127686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-24
[patent_title] => 'Method for validating simulation results of a system as well as equivalence comparison of digital circuits based on said method'
[patent_app_type] => utility
[patent_app_number] => 10/488631
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4691
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/127/07127686.pdf
[firstpage_image] =>[orig_patent_app_number] => 10488631
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/488631 | Method for validating simulation results of a system as well as equivalence comparison of digital circuits based on said method | Aug 28, 2002 | Issued |
Array
(
[id] => 671747
[patent_doc_number] => 07096446
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Hierarchical semiconductor design'
[patent_app_type] => utility
[patent_app_number] => 10/230937
[patent_app_country] => US
[patent_app_date] => 2002-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 9121
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/096/07096446.pdf
[firstpage_image] =>[orig_patent_app_number] => 10230937
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/230937 | Hierarchical semiconductor design | Aug 28, 2002 | Issued |
Array
(
[id] => 680486
[patent_doc_number] => 07089524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-08
[patent_title] => 'Topological vias route wherein the topological via does not have a coordinate within the region'
[patent_app_type] => utility
[patent_app_number] => 10/233202
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 62
[patent_figures_cnt] => 122
[patent_no_of_words] => 56653
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/089/07089524.pdf
[firstpage_image] =>[orig_patent_app_number] => 10233202
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/233202 | Topological vias route wherein the topological via does not have a coordinate within the region | Aug 27, 2002 | Issued |