Search

Jeffrey T. Knapp

Examiner (ID: 7182)

Most Active Art Unit
3205
Art Unit(s)
1722, 3616, 3202, 1725, 3205
Total Applications
712
Issued Applications
662
Pending Applications
22
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1075217 [patent_doc_number] => 06839885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Determining via placement in the printed circuit board of a wireless test fixture' [patent_app_type] => utility [patent_app_number] => 10/225891 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 5634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839885.pdf [firstpage_image] =>[orig_patent_app_number] => 10225891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225891
Determining via placement in the printed circuit board of a wireless test fixture Aug 21, 2002 Issued
Array ( [id] => 7405705 [patent_doc_number] => 20040040000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Device parameter and gate performance simulation based on wafer image prediction' [patent_app_type] => new [patent_app_number] => 10/223931 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3279 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20040040000.pdf [firstpage_image] =>[orig_patent_app_number] => 10223931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223931
Device parameter and gate performance simulation based on wafer image prediction Aug 19, 2002 Issued
Array ( [id] => 958351 [patent_doc_number] => 06957409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method and apparatus for generating topological routes for IC layouts using perturbations' [patent_app_type] => utility [patent_app_number] => 10/219675 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 122 [patent_no_of_words] => 56869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957409.pdf [firstpage_image] =>[orig_patent_app_number] => 10219675 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219675
Method and apparatus for generating topological routes for IC layouts using perturbations Aug 13, 2002 Issued
Array ( [id] => 7394835 [patent_doc_number] => 20040031002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Implementation of networks using parallel and series elements' [patent_app_type] => new [patent_app_number] => 10/217285 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4426 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20040031002.pdf [firstpage_image] =>[orig_patent_app_number] => 10217285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217285
Implementation of networks using parallel and series elements Aug 11, 2002 Issued
Array ( [id] => 7613758 [patent_doc_number] => 06898773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method and apparatus for producing multi-layer topological routes' [patent_app_type] => utility [patent_app_number] => 10/215896 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 122 [patent_no_of_words] => 56431 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898773.pdf [firstpage_image] =>[orig_patent_app_number] => 10215896 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215896
Method and apparatus for producing multi-layer topological routes Aug 8, 2002 Issued
Array ( [id] => 6675975 [patent_doc_number] => 20030061578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Logic optimization device for automatically designing integrated circuits' [patent_app_type] => new [patent_app_number] => 10/212768 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13134 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061578.pdf [firstpage_image] =>[orig_patent_app_number] => 10212768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212768
Logic optimization device for automatically designing integrated circuits Aug 6, 2002 Issued
Array ( [id] => 7413522 [patent_doc_number] => 20040025119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Interactive representation of structural dependencies in semiconductor design flows' [patent_app_type] => new [patent_app_number] => 10/210651 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3371 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025119.pdf [firstpage_image] =>[orig_patent_app_number] => 10210651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210651
Interactive representation of structural dependencies in semiconductor design flows Jul 30, 2002 Issued
Array ( [id] => 933600 [patent_doc_number] => 06981230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'On-chip power-ground inductance modeling using effective self-loop-inductance' [patent_app_type] => utility [patent_app_number] => 10/209081 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5627 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981230.pdf [firstpage_image] =>[orig_patent_app_number] => 10209081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209081
On-chip power-ground inductance modeling using effective self-loop-inductance Jul 29, 2002 Issued
Array ( [id] => 7408361 [patent_doc_number] => 20040019859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method and apparatus for efficient register-transfer level (RTL) power estimation' [patent_app_type] => new [patent_app_number] => 10/206672 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10139 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019859.pdf [firstpage_image] =>[orig_patent_app_number] => 10206672 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206672
Method and apparatus for efficient register-transfer level (RTL) power estimation Jul 28, 2002 Issued
Array ( [id] => 7408469 [patent_doc_number] => 20040019869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Repetition recognition using segments' [patent_app_type] => new [patent_app_number] => 10/208891 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8354 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019869.pdf [firstpage_image] =>[orig_patent_app_number] => 10208891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208891
Repetition recognition using segments Jul 28, 2002 Issued
Array ( [id] => 958340 [patent_doc_number] => 06957407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method and apparatus for detail routing using obstacle carving around terminals' [patent_app_type] => utility [patent_app_number] => 10/206742 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5252 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957407.pdf [firstpage_image] =>[orig_patent_app_number] => 10206742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206742
Method and apparatus for detail routing using obstacle carving around terminals Jul 25, 2002 Issued
Array ( [id] => 940608 [patent_doc_number] => 06973633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Caching of lithography and etch simulation results' [patent_app_type] => utility [patent_app_number] => 10/206691 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4238 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973633.pdf [firstpage_image] =>[orig_patent_app_number] => 10206691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206691
Caching of lithography and etch simulation results Jul 23, 2002 Issued
Array ( [id] => 1021075 [patent_doc_number] => 06892363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Correction of width violations of dummy geometries' [patent_app_type] => utility [patent_app_number] => 10/201101 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 9703 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892363.pdf [firstpage_image] =>[orig_patent_app_number] => 10201101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201101
Correction of width violations of dummy geometries Jul 22, 2002 Issued
Array ( [id] => 7368248 [patent_doc_number] => 20040015798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Reducing verification time for integrated circuit design including scan circuits' [patent_app_type] => new [patent_app_number] => 10/201711 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5693 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015798.pdf [firstpage_image] =>[orig_patent_app_number] => 10201711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201711
Reducing verification time for integrated circuit design including scan circuits Jul 21, 2002 Issued
Array ( [id] => 1037274 [patent_doc_number] => 06877147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Technique to assess timing delay by use of layout quality analyzer comparison' [patent_app_type] => utility [patent_app_number] => 10/200365 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4426 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877147.pdf [firstpage_image] =>[orig_patent_app_number] => 10200365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/200365
Technique to assess timing delay by use of layout quality analyzer comparison Jul 21, 2002 Issued
Array ( [id] => 565192 [patent_doc_number] => 07168060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Method of generating development environment for developing system LSI and medium which stores program therefor using VLIW designating description' [patent_app_type] => utility [patent_app_number] => 10/197891 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 42 [patent_no_of_words] => 13855 [patent_no_of_claims] => 108 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/168/07168060.pdf [firstpage_image] =>[orig_patent_app_number] => 10197891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197891
Method of generating development environment for developing system LSI and medium which stores program therefor using VLIW designating description Jul 18, 2002 Issued
Array ( [id] => 6426447 [patent_doc_number] => 20020184602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Database for designing integrated circuit device, and method for designing integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/196952 [patent_app_country] => US [patent_app_date] => 2002-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184602.pdf [firstpage_image] =>[orig_patent_app_number] => 10196952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196952
Database for designing integrated circuit device, and method for designing integrated circuit device Jul 17, 2002 Abandoned
Array ( [id] => 753565 [patent_doc_number] => 07028281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'FPGA with register-intensive architecture' [patent_app_type] => utility [patent_app_number] => 10/194771 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 41 [patent_no_of_words] => 60597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028281.pdf [firstpage_image] =>[orig_patent_app_number] => 10194771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194771
FPGA with register-intensive architecture Jul 11, 2002 Issued
Array ( [id] => 758141 [patent_doc_number] => 07024651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Partial reconfiguration of a programmable gate array using a bus macro' [patent_app_type] => utility [patent_app_number] => 10/192311 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5220 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024651.pdf [firstpage_image] =>[orig_patent_app_number] => 10192311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192311
Partial reconfiguration of a programmable gate array using a bus macro Jul 8, 2002 Issued
Array ( [id] => 1001864 [patent_doc_number] => 06912702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'Non-linear, gain-based modeling of circuit delay for an electronic design automation system' [patent_app_type] => utility [patent_app_number] => 10/191745 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10972 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912702.pdf [firstpage_image] =>[orig_patent_app_number] => 10191745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191745
Non-linear, gain-based modeling of circuit delay for an electronic design automation system Jul 7, 2002 Issued
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